A 96 channel, 16 bit, 500kHz ADC, and Bus LVDS-based 9U VME readout system for the CALICE electromagnetic calorimeter The CALICE collaboration is studying calorimetry for a future linear collider. Several prototypes of these calorimeters are being built and will be used in beam tests over the next few years. The VME64-based readout system for the CALICE electromagnetic prototype calorimeter will be described. It consists of custom-designed readout boards containing 16-bit, 500kHz ADCs, control, calibration circuitry including 16-bit DACs, timing and data storage. It is designed for an event rate up to 2kHz and can buffer around 2,000 events before VME access is required. The full system for the prototype electromagnetic calorimeter consists of almost 10,000 channels and these are handled by only six such readout boards. The boards make heavy use of Xilinx Virtex-II FPGAs with around 12M gates per board. They have an almost totally generic interface which can be redefined through firmware changes and an array of jumpers. This allows the flexibility to read out an analogue system, using the 96 ADCs per board with LVDS clock and control (as for the electromagnetic calorimeter) or have a purely digital system with up to 544 LVDS pairs available on the front panel (resulting in an I/O rate of over 50Gbits/s at full speed). This latter option is being considered for readout of other calorimeters within the CALICE experiment. Results on the board performance with calibration and calorimeter signals will be presented.