TRIGGER and BACK END FPGA REGISTERS for the CERC.
==================================================

[ * = possible future functionality ]

Dev. Board:
-----------
 0. (0x00) - 
 1. (0x04) - Input Enables
 2. (0x08) - Input Status
 3. (0x0C) - Input Catch
 4. (0x10) - Output Enables
*5. (0x14) - Delayed Trigger Control
 6. (0x18) - 
 7. (0x2C) - 
 8. (0x20) - TestFIFO Data Write

 TestRAM: 0x8000 - 0x8FFC (4kB arranged as 1kx32)
 TestFIFO: D:1k W:32bit

 1. Input Enables - reg_input_en
    - 0: trig_ext0 - LVDS    - on DevBoard: J41(9,10) LVDSIN1
    - 1: trig_ext1 - LVDS    - on DevBoard: J41(7,8) LVDSIN2
    - 2: trig_ext2 - Single  - on DevBoard: SMBCLK J18
    - 3: trig_ext3 - NIM     - on DevIOBoard :NIM0_IN
    - 4: trig_ext4 - NIM     - on DevIOBoard :NIM1_IN
    - 5: trig_ext5 - (LV)TTL - on DevIOBoard :TTL0_IN
    - 6: trig_ext6 - (LV)TTL - on DevIOBoard :TTL1_IN

    [for current testing, trigger input, whatever the source, will probably
     be via trig_ext0]
    
 2. Input Status - reg_input_stat
    Shows the level of a signal
    - 0: trig_ext0_stat 
    - 1: trig_ext1_stat 
    - 2: trig_ext2_stat
    - 3: trig_ext3_stat
    - 4: trig_ext4_stat
    - 5: trig_ext5_stat
    - 6: trig_ext6_stat

 3. Input Catch - reg_input_catch
    Registers a 1 if an input has been high at anytime since the last reset.
    Reset by writing 0
    - 0: trig_ext0_catch 
    - 1: trig_ext1_catch 
    - 2: trig_ext2_catch 
    - 3: trig_ext3_catch 
    - 4: trig_ext4_catch 
    - 5: trig_ext5_catch 
    - 6: trig_ext6_catch 
 
 4. Output Enables - reg_output_en
    - 0: trig_out0_en  - LVDS    - on DevBoard:   LVDSIN1 - J40(9,10)
    - 1: trig_out1_en  - LVDS    - on DevBoard:   LVDSIN2 - J40(7,8) 
    - 2: trig_out2_en  - Single  - on DevBoard:   SMB1 - J16 
    - 3: trig_out3_en  - NIM     - on DevIOBoard: NIM0_IN
    - 4: trig_out4_en  - NIM     - on DevIOBoard: NIM1_IN
    - 5: trig_out5_en  - (LV)TTL - on DevIOBoard: TTL0_IN
    - 6: trig_out6_en  - (LV)TTL - on DevIOBoard: TTL1_IN
    
*5. Trigger Delay Control - reg_trig_dly_ctrl
    - (15:0)  - trig_delay - Delay of trig_dlydX in 10ns steps
    - (22:16) - trig_dlydX_en - swithces speciified trigs to delayed trig
 
 8. TestFIFO Data Write
    Write data to the input port of the TestFIFO.
    Used to fill the FIFO.
    
 

Back End FPGA:
--------------
 0. (0x00) - Trigger Control
 1. (0x04) - Input Enables
 2. (0x08) - Input Status
 3. (0x0C) - Input Catch
 4. (0x10) - Output_Enables
*5. (0x14) - Trigger Counter      
*6. (0x18) - Trigger Osc Period   
*7. (0x2C) - Trigger Burst Control
 8. (0x20) - 
 
 TestRAM: 0x8000 - 0x8FFC (4kB arranged as 1kx32)
 
 0. Trigger Control - reg_trig_ctrl
    Reads back busy_trig status.
    Writing a zero clears Busy
    - 0: trig_active - set when a trigger is recieved, clear by writing a zero.
 
 1. Trigger Enable - reg_trig_en
    - 0: trig_ext - Trigger from DevBoard
    
 2. Trigger Status - reg_trig_stat
    Shows the level of a signal
    - 0: trig_ext_stat - Status of External Trigger Pin
    
 3. Input Catch - reg_input_catch
    Registers a 1 if an input has been high at anytime since the last reset.
    Reset by writing 0
    - 0: trig_ext_catch 

 4. Output Enable - reg_output_en
    - 0: trig_fe0_en  - Enabled Trigger Output to FE0
    - 1: trig_fe1_en  -   
    - 2: trig_fe2_en  - 
    - 3: trig_fe3_en  - 
    - 4: trig_fe4_en  - 
    - 5: trig_fe5_en  - 
    - 6: trig_fe6_en  - 
    - 7: trig_fe7_en  - 

*5. Trigger Counter
    - (31:0): Counts number of triggers sent since last reset.
              Reset by write.

*6. Trigger Osc Period - reg_trig_osc_period
    - (31:0) - Sets time between Oscillator Triggers (trig_osc) in 100ns steps.
    
*7. Trigger Burst Control - reg_trig_burst_ctrl
    Sends Burst of n Triggers
    - (15:0): Number of Triggers to send
    - 16:   Enable Burst Mode (stops all triggers)
    - 17:   Start Trigger Burst



Front End FPGAs:
----------------
 0. (0x00) Config RAM
 39.(0x9C)
 
 40.(0xA0) -  Fake Event Control
 41.(0xA4) - 
 42.(0xA8) -  Input Status
 43.(0xAC) -  Input Catch

 FakeEventRAM: 0x8000 - 0x8FFC (4kB aranges as 1kx32)
  
 
 40. Fake Event Control - reg_fkev_ctrl
     - (9:0): - Event Length
     - 16:  -   Fake Event Mode - when 1, the next trigger will transfer the
              contents of the RAM to the FIFO (normal RAM access is disabled)
              
 42. Input Status
     Shows the level of a signal
     - 0: trig_ext_stat - Status of External Trigger Pin


 43. Input Catch - reg_input_catch
     Registers a 1 if an input has been high at anytime since the last reset.
     Reset by writing 0
     - 0: trig_ext_catch