========================================================================== TRIGGER and BACK END FPGA REGISTERS for the CERC. (includes some FE Registers for now ...) ========================================================================== Updates: 15/04/04 - Modified Catchs to latch on rising edge. - DB Catches added post-enables, all_trig, trigger. - DB - Removed all unused i/o - Updated Output Enables Register - Added post enable catch bits - BE Enable, Status reg name changes to reflect slight new uses 14/04/04 - BE Busy now set by rising edge of trig (not level) - BE Enables - extra trig_in added, osc enable moved - BE Status - added extra trig bits - BE Catch - added post-enables, raw, trigger. Moved osc catch - BE Enable, Status reg name changes to reflect slight new uses 23/03/04 - Added *'s to unimpimented External Trig-In's 16/03/04 - Moved DB Delayed Trigger Control to Reg 6 (0x18) - Added DB Trigger Counter Register (no. 5 = 0x14) 14/01/04 - added Trigger Osc 10/01/04 - added Trigger Counters 9/01/04 - document created [ * = possible future functionality ] [ # = recently changed/added ] -------------------------------------------------------------------------- Development Board -------------------------------------------------------------------------- 0. (0x00) - 1. (0x04) - Input Enables #2. (0x08) - Status #3. (0x0C) - Catch 4. (0x10) - Output Enables 5. (0x14) - Trigger Counter *6. (0x18) - Delayed Trigger Control 7. (0x2C) - 8. (0x20) - TestFIFO Data Write TestRAM: 0x8000 - 0x8FFC (4kB arranged as 1kx32) TestFIFO: Depth: 1k Width: 32bit 1. Input Enables - reg_input_en - 0: trig_ext0 - LVDS - on DevBoard: J41(9,10) LVDSIN1 - 1: trig_ext1 - LVDS - on DevBoard: J41(7,8) LVDSIN2 - 2: trig_ext2 - LVTTL - on DevBoard: J18 SMBCLK 2. Input Status - reg_input_stat Shows the level of a signal # - 0: trig_ext0_i_stat - (LVDSIN1) Ext Trig 0 at input status # - 1: trig_ext1_i_stat - (LVDSIN2) Ext Trig 1 at input status # - 2: trig_ext2_i_stat - (SMBCLK) Ext Trig 2 at input status # - 8: trig_ext0_stat - (LVDSIN1) post enable status # - 9: trig_ext1_stat - (LVDSIN2) post enable status # - 10: trig_ext2_stat - (SMBCLK) post enable status # - 16: trig_all_stat - Combined Trigger pre-stretch logic status # - 17: trigger_stat - Combined Trigger as sent to BE etc status 3. Input Catch - reg_input_catch Registers a 1 if an input has been risen low-to-high at anytime since the last reset. Reset by writing a zero. # - 0: trig_ext0_catch - input catch # - 1: trig_ext1_catch - input catch # - 2: trig_ext2_catch - input catch # - 8: trig_ext0_catch - post enable catch # - 9: trig_ext1_catch - post enable catch # - 10: trig_ext2_catch - post enable catch # - 16: trig_all_catch - Combined Trigger pre-stretch logic # - 17: trigger_catch - Combined Trigger as sent to BE etc. 4. Output Enables - reg_output_en Note: The trigger sent to the BE-FPGA is not disabled here (or anywhere) # - 0: trig_out0_en - LVDS - on DevBoard: LVDSOUT1 - J40(9,10) # - 1: trig_out1_en - LVDS - on DevBoard: LVDSOUT2 - J40(7,8) # - 2: trig_out2_en - Single - on DevBoard: SMB1 - J16 5. Trigger Counter - (31:0): Counts number of triggers since last reset. Reset by write. *6. Trigger Delay Control - reg_trig_dly_ctrl - (15:0) - trig_delay - Delay of trig_dlydX in 10ns steps - (22:16) - trig_dlydX_en - swithces speciified trigs to delayed trig 8. TestFIFO Data Write Write data to the input port of the TestFIFO. Used to fill the FIFO. -------------------------------------------------------------------------- Back End FPGA: -------------------------------------------------------------------------- 0. (0x00) - Trigger Control 1. (0x04) - Input Enables # 2. (0x08) - Status # 3. (0x0C) - Catch 4. (0x10) - Output Enables 5. (0x14) - Trigger Counter 6. (0x18) - Trigger Osc Period * 7. (0x2C) - Trigger Burst Control # 8. (0x30) - Pre-Busy Trigger Counter TestRAM: 0x8000 - 0x8FFC (4kB arranged as 1kx32) 0. Trigger Control - reg_trig_ctrl Reads back busy_trig status. Writing a zero clears Busy - 0: trig_active - set when a trigger is received, clear by writing a zero. 1. Trigger Enable - reg_trig_en - 0: trig_ext0_en - Trigger from DevBoard # - 1: trig_ext1_en - Spare Trigger in # - 24: trig_osc_en - Enables Triggers from internal osc. (see Reg 6) 2. Trigger Status - reg_trig_stat Shows the level of a signal - 0: trig_ext0_i_stat - Status of External Trigger 0 at input # - 1: trig_ext1_i_stat - Status of External Trigger 1 at input # - 8: trig_ext0_stat - Status of External Trigger 0 post enable # - 9: trig_ext1_stat - Status of External Trigger 1 post enable # - 16: trig_raw_stat - Status of Combined Trigger pre-busy logic # - 17: trigger_stat - Status of Combined Trigger as sent to FE # - 24: trig_osc_stat - Status of osc trigger - (not very useful!) 3. Input Catch - reg_input_catch Registers a 1 if an input has been high at anytime since the last reset. Reset by writing 0 - 0: trig_ext0_i_catch - External Trigger 0 at input # - 1: trig_ext1_i_catch - External Trigger 1 at input # - 8: trig_ext0_catch - External Trigger 0 post enable # - 9: trig_ext1_catch - External Trigger 1 post enable # - 16: trig_raw_catch - Combined Trigger pre-busy logic # - 17: trigger_catch - Combined Trigger as sent to FE # - 24: trig_osc_catch - Oscillator trigger 4. Output Enable - reg_output_en Resets to 0x000000FF (i.e. all FE triggers enabled) - 0: trig_fe0_en - Enabled Trigger Output to FE0 - 1: trig_fe1_en - - 2: trig_fe2_en - - 3: trig_fe3_en - - 4: trig_fe4_en - - 5: trig_fe5_en - - 6: trig_fe6_en - - 7: trig_fe7_en - 5. Trigger Counter - (31:0): Counts number of triggers sent to FE since last reset. Reset by write. 6. Trigger Osc Period - reg_trig_osc_period - (31:0) - Sets time between Oscillator Triggers (trig_osc) in 25ns steps. Osc is reset on a write *7. Trigger Burst Control - reg_trig_burst_ctrl Sends Burst of n Triggers - (15:0): Number of Triggers to send - 16: Enable Burst Mode (stops all triggers) - 17: Start Trigger Burst -------------------------------------------------------------------------- Front End FPGAs -------------------------------------------------------------------------- 0. (0x00) - Config RAM .. 39.(0x9C) 40.(0xA0) - Fake Event Control 41.(0xA4) - 42.(0xA8) - Input Status 43.(0xAC) - Input Catch 44.(0xB0) 45.(0xB4) - Trigger Counter FakeEventRAM: 0x8000 - 0x8FFC (4kB arranged as 1kx32) 40. Fake Event Control - reg_fkev_ctrl - (9:0): - Event Length - 16: - Fake Event Mode - when 1, the next trigger will transfer the contents of the RAM to the FIFO (normal RAM access is disabled) 42. Input Status Shows the level of a signal - 0: trig_ext_stat - Status of External Trigger Pin 43. Input Catch - reg_input_catch Registers a 1 if an input has been high at anytime since the last reset. Reset by writing 0 - 0: trig_ext_catch 45. Trigger Counter - (31:0): Counts number of triggers (rising edge's) recieved since last reset. Reset by write.