============================================================================== TRIGGER REGISTERS for the CERC (VME I/F) ============================================================================== Updates: 12/10/04 - This document created (from cerc_registers_rs232.txt): ============================================================================== Intro ------------------------------------------------------------------------------ The trigger modules lives at target 9 in the CERC-VME 'address map'. It used the entire range 1-31 as read-write able. The registers are structured very similarly to the old rs232 setup. The main changes are: Reg 0. moved to Reg 11. Reg 12. bit 0 = Send a trigger (shall we call it a soft-trigger?) bit 1 = Reset trigger module Reg 13. Read FIFO data Reg 14. Read FIFO status Reg 15. bit 0 = QDR_ADDR_19 bit 1 = QDR_ADDR_20 Reg 30. Reads and writes data to the address in Reg 31 Reg 31. (15:0): RAM address (lowest 2 bits ignored) (bit 31): 1 = auto increment address (by 4) after a read or write. Other changes: --------------- RAM now at: 0x0000-0x0FFC Trigger is now a 1-2 clk wide pulse. FE clock/resets left to FED BE code, not touched in trig-module. LED-1 = Syncronised version of trigger sent to FE's LED-5 = Input trigger as send out of the trigger module to all CERCs (called 'trigin' here.) Designator - Register Mapping: ------------------------------------------------------------------------------ 0. 1. Input Enables 2. Status 3. Catch 4. Output Enables 5. Trigger Counter 6. Trigger Osc Period 7. 8. Pre-Busy Trigger Counter 9. Firmware Version ID 10. Firmware Synthesis Date 11. Trigger Control 12. Commands 13. FIFO 14. FIFO Status 15. QDR Test Control ... 30. RAM Data 31. RAM Address Register Discription: ------------------------------------------------------------------------------ 0. 1. Trigger Enable - reg_trig_en - 0: trig_ext0_en - Trigger from DevBoard - 1: trig_ext1_en - Spare Trigger in - 24: trig_osc_en - Enables Triggers from internal osc. (see Reg 6) 2. Trigger Status - reg_trig_stat Shows the level of a signal - 0: trig_ext0_i_stat - Status of External Trigger 0 at input - 1: trig_ext1_i_stat - Status of External Trigger 1 at input - 8: trig_ext0_stat - Status of External Trigger 0 post enable - 9: trig_ext1_stat - Status of External Trigger 1 post enable - 16: trig_raw_stat - Status of Combined Trigger pre-busy logic - 17: trigger_stat - Status of Combined Trigger as sent to FE - 24: trig_osc_stat - Status of osc trigger - (not very useful!) 3. Input Catch - reg_input_catch Registers a 1 if an input has been high at anytime since the last reset. Reset by writing 0 - 0: trig_ext0_i_catch - External Trigger 0 at input - 1: trig_ext1_i_catch - External Trigger 1 at input - 8: trig_ext0_catch - External Trigger 0 post enable - 9: trig_ext1_catch - External Trigger 1 post enable - 16: trig_raw_catch - Combined Trigger pre-busy logic - 17: trigger_catch - Combined Trigger as sent to FE - 24: trig_osc_catch - Oscillator trigger 4. Output Enable - reg_output_en Resets to 0x000000FF (i.e. all FE triggers enabled) - 0: trig_fe0_en - Enabled Trigger Output to FE0 - 1: trig_fe1_en - - 2: trig_fe2_en - - 3: trig_fe3_en - - 4: trig_fe4_en - - 5: trig_fe5_en - - 6: trig_fe6_en - - 7: trig_fe7_en - 5. Trigger Counter - (31:0): Counts number of triggers sent to FE since last reset. Reset by write. 6. Trigger Osc Period - reg_trig_osc_period - (31:0) - Sets time between Oscillator Triggers (trig_osc) in 25ns steps. Osc is reset on a write 7. 8. Pre-Busy Trigger Counter - (31:0): Counts number of triggers sent to FE since last reset. Reset by write. 9. Firmware Version ID - reg_version - ( 7: 0): minor version - (15: 8): major verion - (23:16): 0x09 (Trig target ID) - (31:24): 0x12 (BE module ID) 10. Firmware Synthesis Date - Date/Time Synthesised, in seconds since the epoc (1/1/71) Use normal C routines to decode 11. Trigger Control - reg_trig_ctrl Reads back busy_trig status. Writing a zero clears Busy bit 0: busy_trig - set when a trigger is received, cleared by writing a zero. 12. bit 0: Send a trigger (shall we call it a soft-trigger?) Set to zero before trying to clear the busy bit 1: Reset the trigger module (self clearing) 13. Read FIFO data 14. Read FIFO status 15. bit 0 = QDR_ADDR_19 bit 1 = QDR_ADDR_20 ... 30. Reads and writes data to the address in Reg 31 31. (15:0): RAM address (lowest 2 bits ignored) (bit 31): if set address is auto incremented (by 4) after a read or write. RAM and FIFO ------------------------------------------------------------------------------ RAM: 1kx32: 0x0000-0x0FFC. Not used - For testing purposes only. FIFO: Logs Trig Activity. Depth: 128 Width: 32bit Prior to a trigger this is kept half-full (oldest data replaced by newest data). It is allowed to fill after a trigger and is frozen when full. It gets reset and starts filling again when the trigger-busy is cleared. BE LEDs ------------------------------------------------------------------------------ Note all LED driver signals are stretched for visibilty BE single led - near FPGA: - be_led - flashes to show clocks are running Array - vertical row near center of board (numbered from top): - led_array_0 - - led_array_1 - Trigger - Syncronised version of trigger sent to FE's - led_array_2 - - led_array_3 - - led_array_4 - - led_array_5 - 'Trigin_Out' Trigger sent out of trig-module to all CERCs - led_array_6 - - led_array_7 - - led_array_8 - - led_array_9 -