===============================================================================
TRIGGER REGISTERS for the CRC (VME Interface)
===============================================================================

Updates:
 12/10/04 - This document created (from cerc_registers_rs232.txt):
 07/11/04 - Moved registers around to fit BE/BETrig split
            Room is being made for additional inputs
 11/11/04 - Removed Reg 4 - FE Enables - use BE version now
          - Added Squirt en on desig 29. any read sets squirt mode
            until the fifo is empty.
 18/11/04 - Added BE-Reg Section with new BE-Trig-Enables register (BE-15)
          - Added FE enables, trig-in en and trig-loop-en to be-trig-en reg (BE-15)
          - Renamed Reg. 11 to Control Register (was Trigger Control)
          - Added fanout_en bit to control register (11)
 26/11/04 - Moved fanout-en to BeTrg reg-4
          - Updated LEDs
          - Added all debug registers
          Changes summary: see reg 4, 11, 24,25,26,27, FIFO, LEDs, BETrg
 13/12/04 - Renamed Reg 4 to General Enables, fixed typo bit1=>bit0
          - added reg 4: en-busy-timeout - bit(1)
          - added reg 16: Busy Timeout
 14/01/05 - Added coincedence logic -  reg 19, 20 and enable bits in reg 1
          - Added Pre-Busy Catch register (reg 18)
          - Added input invert register (reg 17)
 20/01/05 - FIFO bits changed
 04/04/05 - Updated FIFO description
 25/05/05 - Added the (bizarrely missing) Squirt Register
 19/08/05 - Renamed reg 15 to 'General Config' register (from QDR control)
            Added TrigFIFO Idle point (see reg 15, FIFO)
 22/08/05 - Moved non-BE-Trg registers (QDR bits in 15, Readout len in 26) to
            BE reg. 15 (see bottom of this file for details)
          - Removed Reg 24, 25 (Were spy registers - don't need anymore)
          - Moved Reg 17 to reg 24
 23/08/05 - Moved busy force to set trigger latch directly, and inhibit busy
            clears. This requires it to be cleared before the trig_busy bit
            cleared to enable triggers.
 25/08/05 - Instated Burst System - see regs 4,7,11,16,17 and note at end.
 26/08/05 - New release BE:0x12006245, BETrg:0x12090010 (TimeStamp: 10:26:54)
 23/10/05 - Added Trig QDR Config register (25) to control the FE like
            functions that send data to the QDR
 24/10/05 - Added fifo test patterns generator - set in reg_config(27:26)
            Fixed reg_config fifo_idle entry here (wrong bits)
 25/10/05 - Added info on new FIFO funcs in FIFO section.


===============================================================================
Legend:

# - reserved/not implimented yet. Also bounded by <>
* - new/updated


===============================================================================
Register Map
===============================================================================
  0.  <unused/reserved>
  1.  Trigger Enables            (trig_enable)
  2.  Trigger Status             (trig_status)
  3.  Trigger Catch              (trig_catch)
  4.  General Enables            (enable)
  5.  Trigger Counter            (trig_count)
  6.  Trigger Osc Period         (trig_osc)
* 7.  Burst Counters             (burst_count)
  8.  Pre-Busy Trigger Counter   (pb_trig_count)
  9.  Firmware Version ID        (fw_version)
 10.  Firmware Synthesis Date    (fw_date)
 11.  Trigger Control            (control)
 12.  Command                    (command)
 13.  FIFO Data                  (fifo_data)
 14.  FIFO Status                (fifo_status)
*15.  General Configuration      (config)
 16.  Busy Timeout               (busy_timeout)
 17.  Burst Timeouts             (burst_timeout)
 18.  Pre-busy Catch             (pb_catch)
 19.  Coincedence AND0 Enables   (cand0)
 20.  Coincedence AND1 Enables   (cand1)
#21.  <Coincedence AND2 Enables>
#22.  <Coincedence AND3 Enables>
#23.  <ExtBeamModeANDOR>
 24.  Signals Inverters          (invert)
*25.  Trigger QDR Configuration  (trig_qdr)
 26.
 27.  Degug Signals Catch        (sig_catch)
#28.  <Sequencer Control         (seq_control)>
 29.  FIFO Squirt Read           (squirt)
 30.  RAM Data                   (ram_data)
 31.  RAM Address                (ram_addr)


===============================================================================
Register Descriptions
===============================================================================

  0. <unused/reserved>
---------------------------------~--------------------------------------------


  1. Trigger Enables             (reg_trig_enable)
---------------------------------~--------------------------------------------
     0: ext0_en
     1: ext1_en
    ...
    15: ext15_en

    16:
    17:
    18:
    19:
    20:
    21: <place holder: trig_raw>
    22: <place holder: trig_cmd>
    23: <place holder: trig_extall>
    24: trig_osc_en     - Enables triggers from internal osc. (see Reg 6)
    25: cand0_en
    26: cand1_en
#   27: <cand2_en>
#   28: <cand3_en>
#   29: <cor_en>
#   30: <extbeammode0_en>
#   31: <extbeammode1_en>


  2. Trigger Status              (reg_trig_status)
---------------------------------~--------------------------------------------
   Shows the current level of a signal
   No reset action

     0: trig_ext0_i_stat   - External trigger 0 at input
     1: trig_ext1_i_stat   - External trigger 1 at input
    ...
    15: trig_ext15_i_stat  - External trigger 1 at input

    16:
    17:
    18:
    19:
    20:
    21: trig_raw           - Trigger prior ot busy and shaping logic
    22: trig_cmd           - Trigger VME command
    23: trig_ext_all       - OR of all external triggers
    24: trig_osc_stat      - Oscilator trigger - (not very useful!)
    25: cand0              - Output coincedance-and unit 0
    26: cand1              - Output coincedance-and unit 1
#   27: <cand2>
#   28: <cand3>
#   29: <cor>
#   30: <extbeammode0>
#   31: <extbeammode1>


  3. Trigger Catch               (reg_trig_catch)
---------------------------------~--------------------------------------------
   Registers a 1 if an input has been high at anytime since the last reset.
   Useful for checking if a signal has happened
   Reset by writing 0

     0: trig_ext0_i_catch  - External trigger 0 at input
     1: trig_ext1_i_catch  - External trigger 1 at input
     |   ...
    15: trig_ext15_i_catch - External trigger 15 at input

    16:
    17:
    18:
    19:
    20:
    21: trig_raw           - Trigger prior ot busy and shaping logic
    22: trig_cmd           - Trigger VME command
    23: trig_ext_all       - OR of all external triggers
    24: trig_osc_catch     - Oscilator trigger - (not very useful!)
    25: cand0              - Output coincedance-and unit 0
    26: cand1              - Output coincedance-and unit 1
#   27: <cand2>
#   28: <cand3>
#   29: <cor>
#   30: <extbeammode0>
#   31: <extbeammode1>


  4. General Enables          (reg_enable)
------------------------------~------------------------------------------------

     0: fanout_en       - Enable J0 Fanout  - i.e. enable Crate-Trigger
     1: busy_trig_to_en - Trigger busy timeout counter enable.
*    4: burst_en        - Burst mode enable - send fixed numbers of triggers
*    5: bto_en          - Burst timeout enable - stops burst if takes too long
*    6: ibto_en         - Inter-burst timeout enable -
                          applies deadtime between bursts
#    7: <bburst_en      - Burst-burst mode enable - bursts of bursts>
     8: coinc_en        - Trigger coincendance logic enable
#    9: <cmode_int_sel  - Coinc ModeInt select 0: cand0, 1: cand1>
#   10: <cmode_ext_sel  - Coinc ModeExt enable 0: ModeInt, 1: use input>


  5. Trigger Counter          (reg_trig_count)
------------------------------~------------------------------------------------
   Counts number of triggers sent to FE since last reset (32 bit).
   Reset by write.


  6. Trigger Osc Period       (reg_trig_osc)
------------------------------~------------------------------------------------
   Sets time between Oscillator Triggers (trig_osc) in 25ns steps (32 bit).
   Reset by a write.


* 7. Trigger Burst Counters   (reg_burst_count)
------------------------------~------------------------------------------------
#   <(31:16):  B-Burst Count - Number of bursts>
     (15: 0):  Burst Count - Number of trigs in a burst

   See reg 16, 17 for busy and burst timeouts.


  8. Pre-Busy Trigger Counter (pb_trig_count)
------------------------------~------------------------------------------------
   Counts number of triggers sent to FE since last reset (32 bit).
   Reset by write.


  9. Firmware Version ID      (reg_fw_version)
------------------------------~------------------------------------------------
   (31:24): 0x12 (BE module ID)
   (23:16): 0x09 (Trig target ID)
   (15: 8): major version
   ( 7: 0): minor version


 10. Firmware Synthesis Date  (reg_fw_date)
------------------------------~------------------------------------------------
   Date/Time firmware was synthesised, in seconds since the epoc (1/1/71)
   Use C time.h routines to decode


 11. Control                  (reg_control)
------------------------------~------------------------------------------------
   Control and (special) Status register.

   0: busy_trig      - Trigger Busy - set when a trigger is received.
                       Cleared by writing a zero.
*  1: busy_force     - Force a Busy - writing a 1 generates a forces a busy,
                       Note: Setting this without an existing trig_busy will
                       generate a trigger.
                       To re-enable triggers, clear this, then clear busy_trig.
*  4: busy_burst     - Burst Busy - is set when Burst-Mode starts/ends(reg 4.2)
                       Clear to start a burst.
                       If Inter-Burst timeout is enabled, this is auto-cleared
                       when IB timesout to start new burst.
*  5: busy_bto       - Burst Timeout Busy - set when burst stopped due to
                       timeout. If Inter-Burst timeout is enabled, this is
                       auto-cleared when IB timesout to start new burst.
*  6: busy_ib        - Inter-Burst Busy - set when when in inter burst phase
#  7: <busy_bburst   - B-Burst Busy - set when B-Burst ends>


 12. Commands                 (reg_command)
------------------------------~------------------------------------------------

   0: Send a BE-Trig Trigger - i.e. crate trigger.
           Set to zero before trying to clear the busy
   1: Reset the trigger module (self clearing)


 13. FIFO data                (reg_fifo_data)
------------------------------~------------------------------------------------
   Get data out of trigger fifo.
   See "RAM and FIFO" section below.


 14. FIFO status              (reg_fifo_status)
------------------------------~------------------------------------------------
      17: fifo_full     - FIFO full-flag
      16: fifo_empty    - FIFO empty-flag
   (9:0): fifo_depth    - Depth counter


 15. General Config           (reg_config)
------------------------------~------------------------------------------------
*  (31:16) Trig Fifo Idle point select
*  ( 1: 0) FIFO Test Pattern Mode (0=off, 1=constant val, 2=oscillate, 3=count)



 16. Busy Timeout             (reg_busy_timeout)
------------------------------~------------------------------------------------
   Sets time between Trigger and busy auto clear in 25ns steps (32 bit).
   Enabled by reg_enable:busy_timeout_en (4,1)
   Cleared by write (or a trigger).


*17. Burst Timeouts           (reg_burst_timeout)
------------------------------~------------------------------------------------
*  (31:16) Inter-Burst(IB) Timeout (ibto) - in 1ms steps
*  (15: 0) Burst Timeout (bto) -  in 1ms steps

   See reg 4, 7.


 18. Pre-busy Catch           (reg_pb_catch)
------------------------------~------------------------------------------------
   Catches all trigger input sigs (as in reg_trig_status) until the busy.
   Cleared by a write.


 19. Coincedence AND0 Enables (reg_cand0)
------------------------------~------------------------------------------------
   (31:16)  Input inverts
   (15: 0)  Input enables


 20. Coincedence AND1 Enables (reg_cand1)
------------------------------~------------------------------------------------
   (31:16)  Input inverts
   (15: 0)  Input enables


#21. <Coincedence AND2 Enables>
------------------------------~------------------------------------------------


#22. <Coincedence AND3 Enables>
------------------------------~------------------------------------------------


#23. <ExtBeamModeANDOR>
------------------------------~------------------------------------------------


 24. Inverters                (reg_invert)
------------------------------~------------------------------------------------
   Inverts input triggers and the cand outputs (and more?)
   Using the cand out inverts along with cand in inverts can create OR gates

      25: inv_cand1_out
      25: inv_cand0_out
   (15:0) External trigger inputs invert for non-coincedence mode


 25. Trigger QDR Configure    (reg_trig_qdr)
------------------------------~------------------------------------------------

  (18:16) Readout Sync Delay (25 ns steps)
  (15: 0) Frame Sync Delay (12.5 ns steps)


 26.
------------------------------~------------------------------------------------
<unused>


 27. Debug Signals Catch      (reg_sig_catch)
------------------------------~------------------------------------------------
      20: FE-0 Trigger as sent  (BEEFY)
      19: Synchronous Trigger   (BEEFY)
      18: FE-0 readout_sync_out (BEEFY)
      17: FE-0 frame_sync_in    (PHEOBE)
      16: FE-0 readout_sync_in  (PHEOBE)
   (15:0) FE-0 Data into BE     (PHEOBE)


#28. <Sequencer Control       (reg_sequencer)>
------------------------------~------------------------------------------------

      31: seq_reset     - Reset Seq (set counter to zero, stop loop, clear go)
      30: seq_go        - Start Seq running
      29: seq_loop_en   - Enable seq infinite run by looping
# (29:26) <possibel increase in sequencer length
  (25:16) seq_count     -
  (15: 0) seq_en        - Sequencer outputs enables

 29. FIFO Squirt Read         (reg_squirt)
------------------------------~------------------------------------------------
     Starts a read of all Trigger FIFO Data as a single command, with the
     contents of the *entire* FIFO serialised out as the payload data.
     You should program the serial data length depending on FIFO depth.


 30. RAM Port Data            (ram_data)
------------------------------~------------------------------------------------
     Reads and writes data to the address in Reg 31.
     RAM is only used for testing at present.
     See "RAM and FIFO" section below.


 31. RAM Port Address         (ram_addr)
------------------------------~------------------------------------------------
     (   31) if set address is auto incremented (by 4) after a read or write.
     (15: 0) RAM address (lowest 2 bits ignored) (higher order bits might not
             be used either.



===============================================================================
RAM and FIFO
===============================================================================

RAM:  1kx32: 0x0000-0x0FFC. Not used - For testing purposes only.

FIFO: Log Trig Activity. Depth: 1023  Width: 32bit
      Fifo is filled with the data as in Reg 2. Trigger Status.
      Prior to a trigger the FIFO is kept filled to a level specified in
      reg_config(15, 25:16).
      It is allowed to fill completely after a trigger and is frozen when full.
      It gets reset and starts filling again when the trigger-busy is cleared.

*New FIFO functions:
*1.FIFO data is now bounded by header and footer words.
   Header (2 words): 0x12345678, Trigger Number
   Trailer(1 word) : 0xDEFCBA98.
   <start-word><trig-number><trigger-data0>...<trigger-dataN><stop-word>

*2.FIFO can have data replaced with test sequences (see Reg 15. Config(1:0) )
   pattern 0: Real data, for normal running
   pattern 1: Constant - 0xf1e2d3c4 in every location
   pattern 2: Oscillating - 0x55555555, then 0xAAAAAAAA. repeated
   pattern 3: Counting - count since end of last busy

*3.QDR Mode:
   This is set when BE Reg 15.Trigger Enables has bit 12 set (trig_into_fe0_en)
   This enables trigger data to replace FE0 data. Also needs to be enabled (and
   probably needs all the other FE's disabled).
   In this mode all trigger data ends up in the QDR (I hope) and cannot be
   accessed via reg reads or squirt.




===============================================================================
BE LEDs
===============================================================================
Note all LED driver signals are stretched for visibilty

 BE single led - near FPGA:
 - be_led - flashes to show clocks are running

 Array - vertical row near center of board (numbered from top):

  1: BE Trigger
  2: Trig Coinc-AND0
  3: BeTrg Trigger-Out (to fanout)
  4: Trigger in (from J0 A4/B4)
  5: Trigger in post enable
  6: FE0 Trigger (as sent out of pin)
  7: BeTrg Trigger-Out pre-busy
  8: FE5 Trigger (as sent out of pin)
  9: BeTrg serial command to VME
 10: BeTrg Busy
 11: <not under our control>


===============================================================================
BE Section Info
===============================================================================

These are extras added to the original FED set

 15. Trigger Enables - reg_fe_trig_en
     Resets to 0x000000FF (i.e. all FE triggers enabled)

    (30:16) test_mode_readout_len (was reg 26)
*   (   12) trig_into_fe0_en - enables trigger data to replace FE0 data
*   (   11) QDR Address line 20 (was reg 14.1)
*   (   10) QDR Address line 19 (was reg 14.0)
*   (    9) crate_trig_loop_en - enable internal crate-trig loopback (bypass j0)
    (    8) crate_trig_in_en - enable j0 trigger input
    ( 7: 0) trig_feN_en - enabled triggers to FEs



===============================================================================
Burst System Notes
===============================================================================

This details how the burst system is designed/intended to work.
It may not be true of how it works in reality.
(Note: trig_busy_timeout is configured entirely separately and is independent
of the burst system)
reg_enables is used to set which components are used in the burst:
'burst_en'  primary burst enable - is also needed for all other burst options
'bto_en'    burst timeout enable - will end a burst if it takes too long.
'itbo_en'   inter-burst timeout - enables a repeditive burst with a
             inter-burst   delay between each burst
Count/Timeout registers:
reg_burst_count:  configures the number of triggers in a burst
reg_burst_timeout (31:16) sets the burst timeout (bto) in milliseconds.
reg_burst_timeout (15:0) sets the inter-burst timeout (ibto) in milliseconds.


When starting a burst, configure all burst parameters (as set-out above).
Then set the 'burst_en' bit (reg_enables:4,4). Clear busy_force if needed.
Setting 'burst_en' will bring up the 'busy_burst' signal and stop triggers.
When ready, clear 'burst_busy' and any other busys (easist by writing 0 to
reg_control).
Monitor burst activity by reading reg_control:
- 'busy_burst' is set while waiting for a burst to start,
   and again when it finishes.
- 'busy_bto' is set if the burst terminates due to a burst-timeout
- 'busy_ib' is set during the inter-burst busy period if the
   inter-burst-timeout is enabled.
These can be cleared during a burst cycle by writing a 0.
Clearing 'busy_ib' will force the start of the next burst.
All busy's are cleared when a new burst starts.

Note that a rising timeout busy can generate a trigger, so the last trigger of
every burst should be ignored/discarded.