general
=======
o Test speed of new switch
o Test different mplex values (=data lengths) in different FEs

hi-priority
===========
o Set up control of SM for spill runs (when to end, etc)
  using module at end of list and control subrecords from
  writer, etc. OBSOLETE NOW WRITER DOES NOT NEED TO END RUN?
o Why does crcNoise screw up DAC values in HABs 6-11?
o Where does ASIC event in ahcXmLed come from???

hardware
========
o Add termination resistors for trigger fanout to ECAL production
  boards if needed

PCs
===
o Set up nfs mounts within router local network
o Allow choice of one or two CPU operation on calice01
o Find out about ipcclean

FE firmware
===========
o Ensure all unused bits in configuration read back as zero
o Speed up HOLD, TCALIB to 320MHz
o Time FrameSyncOut and ReadoutSyncOut off trigger trailing edge
o Fix missing flags for last ADC sample
o Reduce FE-to-FE jitter?
o Document spy register and add 160(320)MHz phase to it

BE firmware
===========
o Ensure all unused bits in configuration read back as zero
o Carefully time trigger falling edge
o 2k events in buffer and side FIFOs
o Clear of QDR and side FIFOs

BETrg firmware
==============
o Ensure all unused bits in configuration read back as zero
o Enable veto of oscillator by activity
o Have dead time for ~1us after activity
o Time FrameSyncOut and ReadoutSyncOut off trigger trailing edge
  for BE-Trg data
o Allow trg data to be diverted to any FE, not just FE0

records
=======
o Remove vlinkSpill info from CrcReadoutConfiguration
o Update to new BE-TRG firmware
o Clean up vmeAdm1025/LM82
o Move crc/Trg... to trg/Trg...
o Rename preEvent to trigger throughout and postEvent to event
o Allow (in principle) multiple spills/transfers per acquisition
o Allow more space for emc in run types

daquser
=======
o Clean up socket error handling; allow only 100 loops with no data
  before crashing out
o Sort out State Machine display
o Divide RunWriter into slow and data; make slow one file for
  startUp->shutDown, only use run number when not dummy write
o Move from data/dat to data/run
o Make event rate in runMonitor more intelligent; rolling average?
o Use RcdUserBase::doPrint consistently
o Add error/termination control using a final module in the sequence.
  Others need to add information i.e. RO->RW
o Move RO modules onto the end of a (or more than one?) one-way socket
  and put HstGeneric and RunWriter into these sockets
o Make CrcFakeDevice with same (complicated) interface so as to load
  record correctly for daqTest runs. Make alive method return standard
  5,7,9,12,15,17,19 CRCs.
o Use SetBit(TH1::kCanRebin) method of TH1 to automatically rebin when
  outside range. This is for HstRecord.hh.
o Config checks for AHCAL VFE data
o Add CRC slow readout plots
o Change HstHist to refill existing hist. If it works, use throughout
o Add trigger and acquisition hists to HstRecord
o Add VFE DACs to HstCheck. Find ShiftReg bug at start of run.
o Add acquisition count to RunCount/runMonitor. Allow runMonitor sleep
  time to be an argument
o Clean up VFE shift reg handling
o Add config for Ahc stage settings
o Clean up various beam/cosmics configs
o Run sequences!
o Add mega-TH2F hist for each channel; restrict to slots 5,7,9,12,15,17,19
  and rename to HstCrcSignal
o read19 run where number of channels is variable (default 19)
  and oscillator gives lengthening delays
o Put in alternative HOLD shifts for various FEs
o Implement a read19 panic run
o Fake up all the data volumes so as to allow daqTest
o Fix x2 bug in HstRecord

online
======
o Clean up TrgReadout triggering to be reliable, BUSY until needed, etc.
o Find problem causing board temperature crashes from LM82
o Resusitate forking
o Parallel read for transfers
o In transfer, read next event before reading record from socket
  Care with preevents.
o Reset changes to CrcVmeDevice/CrcReadout for vlink speedup and
  put protection back in (a la original)
o Track down "wrong CRC" error a la Log1128217723Crc1.err; make alive
  more robust (alternate reads of Firmware and something else?)
o Figure out good inheritance (or whatever) for Trg/Ahc/EmcReadout
  from CrcReadout (and Ahc/TrgVmeDevice?)
o Track down kernel driver errors (three in total; one longstanding,
  one since the BLT speedup, report by Kostas on 14/10/05).
o Allow single CPU operation in case of interference with SBS driver
o Fake up spills using bool in shared memory accessed by CrcVmeDevice
  method; NO! Use simple time() in method of CrcVmeDevice
o Check for label=1 when writing configuration
o Check on use of vmeAdm1025 and vme when doing slow readout, etc; make
  consistent
o Use VFE type info to set enable bits for Emc, Ahc, beam and cosmics
  runs
o Do bt_info for the relevant PCI device only in CrcReadout
o Get trg data in Vlink working with other ADC data
o Figure out how to get BE write and read to agree wrt trg and fe
  enables

recent
======
o Enable BETrg fast data for most runs
o Turn on time limits for triggers/spills
o Spills tests at DESY
o sktXxxReadout with event pre-read (TrgReadout does nothing on event)
o sktHstGeneric
o Remove use of ROOT for monitoring input
o Resusitate TrgConfiguration; how to label trigger position?
o Allow different spill mode per configuration (or at least mask)
o ECAL flat files to label CRCs and emcExpert run
o Run sequences
o ECAL stage PC communication
o Spill 5/12sec faked


