Minutes of CALICE Electronics Phone Meeting, 16/12/02 ===================================================== Present: Adam Baird, Dan Bowerman, Jon Butterworth, Paul Dauncey, Rob Halsall, Dave Price, Matthew Warren, Osman Zorba Minutes: Paul News: Paul received an email from Jean-Claude Brient (the CALICE spokesman) stating that the Orsay engineers responsible for the VFE and VFE-PCB had said LVDS might be too difficult to implement on their board. This would clearly be a major disruption to our plans and would have significant schedule implications. However, as Jean-Claude (by his own admission) is not an electronics expert, it was thought best to get the details directly from Julien Fleury. Adam and Rob will contact him by email to try to determine what the problems are and how big an issue this will be. Matters arising: From the last minutes, the discussion of item 3 from Rob's list stated Paul would look into safety requirements. He had found the person at Fermilab but had not got an answer yet. [Note added after the meeting: Paul was sent a website URL for the Fermilab test beam area which contains some safety documents. This is now linked from the bottom of the CALICE-UK home page.] Item 11 had two points. The number of I/O pins needed for the FE is discussed later. The lead time for ordering the components is probably 6-8 weeks for all, so these need to be started in the New Year. This sets the timescale for deciding the FE FPGA component. We will order enough for two boards. Under "FE-BE interface", Rob is to circulate the description of the command protocol as used by the CME FED FE for the configuration data path. Under "Trigger logic", the issue of how to handle three VME interupts was still outstanding. Rob reported there are 8 control lines between the BE and VME FPGAs, but only two are currently used. It would be straightforward to activate these as interupts but it would require changing the VME FPGA firmware, which we had hoped would not need to be touched. It would be better for this to become incorporated into the CMS firmware as then further updates from the CMS side could be used directly by us. An alternative is to poll for the occurances which would cause the interupts instead; Paul was not sure if this would be sufficient. Under "Schedule", Paul got a VME crate added to the CMS order. It will cost 8.5kCHF (~4kpounds) which is under the 6kpounds in the budget for this. The delivery date is not known but it will be well before we would have boards to plug in. It will be delivered to CERN and so will need to be shipped back to the UK (along with several of the CMS crates, apparently). Matt had seen one of the crates at CERN. The power supply sits at the top, behind the J1 connectors, but leavs access to J0 and J2 clear. It had 4 6U slots without a separating panel from the rest of the crate. Layout status: Adam needs to change the existing layout to make it more modular so it can be step-and-repeat'ed 8 times. He will need help from Chris Day. The first order layout exists otherwise. There is physically room to add the extra components needed for negative LVDS but it will make the layout painful; it would not be a showstopper but would result in a less good board. FE status: The aim is to fix the signal-pin allocations by the end of January so the layout can proceed. It was thought unlikely this would be a significant constraint but some block-level design should be done to get this. Some information on the I/O was requested by IC; specifically the CMS FE-BE protocol as intrepreted by the FE FPGA and the entity information for the FE. For the latter, this divides into the FE-BE lines (which are already defined) the ADC and DAC control, and the cable LVDS. Adam has notes covering these items but these are not in a sharable state at present. The ADC/DAC and cable signals will be spread down the left-hand side of the FE FPGA, with these signals interspersed in stripes of pins. He hopes for a first layout this week. Adam has estimated the I/O count; see spreadsheet. The I/O count was as follows. Each connector has 68 pins; of these 12 are for the 6 differential ADC inputs, and 2 are for the DAC output. The other 54 will be connected directly to the FPGA for use as LVDS; 24 are used for the VFE-PCB and the other 30 are spares. As each FE controls two connectors, this is 108 LVDS pins needed. Each ADC needs 10 control lines, for a total of 60 pins. Each DAC needs 3 control lines, for a total of 6 pins. Finally, there are 14 lines for the FE-BE interface. This gives a total of 188 pins. The FG456 smaller FPGA has at least 200 lines, which leaves almost no margin. This means either it might be necessary to use the larger FG676, as for CMS, or to combine some of the low-level ADC control signals into one. This can be done without removing significant flexibility. Paul asked if there was a data size limit on the FE-BE data link. Rob thought the CMS raw data format was around 48kBytes (which would be well above any CALICE data size) although he needs to check the figure. BE trigger status: Paul asked about the output trigger distribution from the triggering readout board to the other slots in the crate. There was a discussion in the previous meeting about making a small back-of-crate card which would split the trigger signal to allow one cable per slot from the card to each of the remaining slots in the crate. This would be needed as there are only 14 spare pins, i.e. 7 LVDS signals, available on J0. There are more on J2; this has 64 pins for the trigger logic I/O matching the 16 in and 16 out LVDS signals of the NIM-LVDS board. In addition, there are another 26 pins unused. If the cable from the J2 connector can be split, then these 26 could be used for the trigger output. This would allow 13 LVDS signals and so feed to 13 slots. This is probably sufficient. Next meeting: Face-to-face on Tue 14 Jan, UCL, starting at 1pm.