Minutes of CALICE Electronics Phone Meeting, 03/02/03 ===================================================== Present: Adam Baird, Paul Dauncey, Rob Halsall, Martin Postranecky, Dave Price, Matthew Warren Minutes: Paul Fallout from Orsay: There were several issues which were discussed at the meeting at Orsay on 21/01/03: o) The VFE-PCBs will be built to hold a 2x3 array of silicon wafers. However a layer is 3x3, so a complete layer will consist of two VFE-PCBs, with the second only half populated. The original connector specification required two identical connectors per VFE-PCB, each controlling half the channels. For the half populated board, only one cable would have been needed. However, because of space constraints, there is a push to reduce the number of I/O pins and there will now be only one connector for each VFE-PCB. This will carry the signals from all channels and so each cable will now have signals from twice as many VFE chips as previously, i.e. 12 rather than 6. For the half populated board, half the analogue signal will be unused. This has several effects for the UK board as we cannot double the ADC density so the board will only be able to take 8 of the larger cables, rather than 16. However, a half populated cable would then not use half of the ADCs allocated to the cable and so we would need more boards, 8 rather than 6, with an increased cost of around 12k. Various work-arounds were proposed. Adam favours keeping a double row of connectors and using jumpers to allow either a full cable on one connector or two half populated cables on two connectors. There are 6 analogue channels which need to be switched (see figure) plus some number (as yet undefined) of serial register outputs and a single line allowing the FE FPGA to detect the jumper configuration. It would be very useful if a single header with all the necessary jumpers could be made and so placed in one go. Other possibilities are a patch panel (which could reroute the signals for two half populated cables into a full cable as well as distribute the VFE-PCB power and provide strain relief) or daisy-chaining pairs of VFE chips on the fully populated boards to give the same number of analogue channels but with twice the multiplex length for the full boards. The former would introduce extra connectors and the latter would cause a longer readout time so both were disfavoured. o) The connector choice for the VFE-PCB is still to be fixed. The connectors shown at Orsay were thought very flimsy and unlikely to be robust enough. Adam had sent Julien an email with details of a connector which might be usable. It has two formats; either 71 communication pins or 59 communication plus 6 power. A rough count of the required pins at Orsay showed the number should be less than the 68 in the readout board SCSI connector so the 71 pin option should work, but whether the number will fit within the 59 pins needs some thought. The size of the connector is 5.6mm, of which the shroud is a major contribution. The connector can be bolted onto the PCB (although they would need to provide countersunk holes) and so would be mechanically robust. The shroud can allow the cable to be split into two directions, which might be useful if the power is supplied through the same cable as this means it could be kept separate from the UK boards. Adam has contacted a company for a quote to make the full 60 (plus spares) cables and connectors and they will send four sample sets of connectors to him. o) The signal voltage specifications were firmed up. All LVDS will be standard with no negative offsets; the VFE-PCB now has +ve power anyway so they realised converting the level on the VFE-PCB would be sensible. The analogue signal levels will be 0 +/- 3V which, with 100ohm termination, will become 0 +/- 1.5V. This might be tuned a little to allow it to be fed directly into the ADC, which means something more like 0 +/- 1.2V. The DAC output voltage will ideally be defined to be identical to the ADC input range, so the DAC output can be fed directly to the ADC. o) The definition of which pin takes which signal was not decided. However, Adam will allocate pins as needed to ease his layout and will try to get Julien to agree to an equivalent order. In principle, any variations can be taken out in the cable but while this would be easy for a bundled cable, flat twisted pair would be a mess, so a clean allocation is by far preferable. o) The homework on investigating beam timings, etc, had not been done so there was no new information on how many events will need to be buffered per beam burst. Hence, we have to continue to assume the 8MByte memory, which should store around 2k events, will be needed. Rob said 4MByte memories are now available with the same footprint as the 1MByte components used in pairs on the FED. The extra two address lines needed per memory component from the BE could be taken from the ~10 TTC connections as these will not be needed for CALICE. o) The possible use of the UK boards for HCAL readout is still very uncertain. There seems to be little progress on designing an analogue HCAL equivalent of the VFE-PCB so that the chance of having a prototype of this board before we need to go to production is small. The digital HCAL people are thinking of designing a separate board for their readout. This will be discussed at an HCAL meeting on Fri 28 Feb (see below). Upcoming Meetings: There are three upcoming CALICE meeting announced recently by Jean-Claude Brient. These are: o) CALICE-HCAL, Ecole Polytechnique on Fri 28 Feb. There will be a discussion on HCAL readout so it seems important that we have someone there to give the UK input. Adam said he thought he might be able to go. [Note added after meeting; Paul is also able to go.] o) CALICE-ECAL, London on Tue 18 Mar. This could be either UCL or IC. It is during term time so the problem will be finding a room for ~40 people. Both sites should continue to look into this. o) CALICE general, Amsterdam on Mon 31 Mar. This is before a 4-day LC workshop in Amsterdam on Tue to Fri of that week. Schedule: Jean-Claude had presented a rough outline of the schedule at the Orsay meeting which indicated the ECAL electronics would be needed for cosmic tests in "spring 2004" and for a DESY test beam in "summer 2004". The schedule presented by Paul (page 7 of his talk) at the meeting indicates we would be too late, by around two months, to meet these dates. One obvious place to try to shorten the schedule is the six months of testing this summer. However, we would need to know when the VFE prototype tests can be done before assuming this test period can be shortened. One other place where a saving on time might be possible is in the month of redesign and two months of relayout for the production boards. If the prototypes are close enough to what we need, this period might shorten substantially (although we will not know this for some months). The prototype testing period is likely to be limited by the firmware designs as although the hardware can be tested using embedded logical analysers in the FPGA's, we would also want to check the board runs as required and so test VME access speeds, etc. BE-trigger: Matt went through his diagram of the functional blocks of the BE-trigger logic. The biggest issue is how to handle the trigger path itself; should it be synchronised in the BE or left asynchronous throughout this FPGA? The FPGA's are not ideal for asynchronous logic and can give glitches on the outputs, although the implementation needs to be tested to see if it could be made to work. Asynchronous logic might be susceptible to latencies which are temperature dependent, although it is unlikely these would be significant at the several ns level. There is a possibility of having the asynchronous logic on an external back-of-crate board in discrete components although the I/O required might be too high. Matt's diagram also included a sequencer and sink to play and record data through the trigger logic, which was thought a very useful feature. The triggers to the HCAL were shown as having 2 adjustable delays. If needed, this could be broadened to all 12 lines having individually adjustable delays. The count of I/O pins available on J0 and J2 is in the minutes of the phone meeting on 16/12/02, under "BE trigger status". Status: An email Q&A discussion between Rob and DaveM has been summarised in a text file on the usual web page. Dave P looked up some prices for the FE FPGA's. From Insight, for an order of 100 components of speed grade -4, he was quoted: FG456/250 44.5 pounds, FG456/500 76 pounds, FG456/1000 110 pounds, FG676/1500 156 pounds and FG676/2000 222 pounds. In fact, the quote says these prices hold even for smaller quantities. Due to their negotiations for CMS, RAL can get lower prices; from Impact, they have be quoted 130 pounds for the FG676/1500 and 185 pounds for the FG676/2000. The components have a 5 week delivery time. Two CMS FED prototype boards have now been assembled and are under test at RAL. The power supply hot-swap is up and running, the JTAG internal tests are OK and the JTAG VME tests will be done in the next week. Rob will organise the CMS firmware design engineers to give presentations to us around the last week of February. This will probably be a half day at RAL; we could use the other half to have a CALICE meeting. Demo boards: Virtex-II demo boards are around 400 pounds. This is not a trivial amount given our budget but if it would help the firmware development, we should get one (or more). IC have one for CMS use but it is unlikely we would get a lot of time with it. Next meeting: Phone meeting on Tue 18 Feb, starting at 2pm.