Minutes of CALICE Electronics Phone Meeting, 18/02/03 ===================================================== Present: Adam Baird, Dan Bowerman, Paul Dauncey, Rob Halsall, Dave Mercer, Martin Postranecky, Dave Price, Matthew Warren Minutes: Paul News: DaveM will be at SLAC from 20/02-06/03. Matt will be away (on honeymoon; congratulations!) from 08/03-29/03. Julien has checked the mechanical clearance between the VFE-PCBs and it seems there is 8mm, which is sufficient for them to use the same 68-pin SCSI connector as on the readout board. It is not clear if they will need to bring power in through this connector; if so, the cables will still need to be custom-made. The number of pins to be used will be determined by the VFE-PCB needs and is not yet decided. It is important to check the FPGA design tools being used at the various sites are the same versions if the firmware is to be designed in multiple places. The versions used are as follows: UCL; Base: Advantage 5.3, but components have been upgraded to: HDL Designer: 2002.1b ModelSim SE: 5.7a Leonardo: 2002e Manchester; Advantage ? HDL Designer: 2001.5 ModelSim SE: 5.6e Leonardo: 2001_1d.45 XILINX 5.1i service pack3 Imperial; Suggest Advantage 5.4 RAL; Will move to Advantage 5.3 soon Latest downloadable; Advantage 5.4 HDL Designer: 2002.1b ModelSim SE: 5.7b (note, Advantage 5.4 comes with 5.6f) Leonardo: 2002e There was a firmware design "tutorial" day tentatively scheduled at RAL for today, but this did not get firmed up. We also would like talks from the CMS firmware designers on the FED FPGA code. We will try to combine these into a full day at RAL, with the tutorial in the morning and the design talks in the afternoon; Rob will organise this. A date of Tue 11 Mar was tentatively set; Matt will not be able to attend and Paul can only come for the afternoon. If we cannot get the CMS people for the talks on that day, then the tutorials should go ahead anyway and we will hold our regular meeting at RAL in the afternoon instead. Demo boards: The question of whether to invest in Virtex-II demo boards was raised at the last meeting. The critical question is whether they will help with progressing the firmware designs. It was thought that at least UCL should buy one, to help with the asynchronous design for the trigger logic. They should buy the FG256/1000 version, with a cost around 500 pounds. RAL has three put they are shared with several other projects. Imperial has one shared with CMS. The original ones were engineering samples (but have since been upgraded) but any purchased now would have the final FPGA versions. There was a discussion on whether Chipscope (an embedded logic analyser) is also needed; RAL already have it. It is used for hardware checks, not firmware development (the most critical area right now) so it doesn't seem it would help progress the designs or be needed in the Universities. In addition, it was thought that the license is site-wide, so it seems more suitable as a rolling grant purchase for the University groups. However, as it is only around 200 pounds, if there is an actual need for it, then we should get it for any group which can make use of it. FED status: The JTAG connectivity tests are complete and the board works with JTAG parallel-3 cable. Chipscope is now being used to check the FPGAs. It will be a few weeks before the firmware for the VME and BE FPGAs is complete. DaveM will talk to the RAL VME firmware designers to give them the entities needed to implement VME interrupts. One recent problem has been that the FPGA load chain has a limit of 30 FPGAs while the board requires 36. This would not be an issue for CALICE as there are only 10 FPGAs on each board. Layout status: The schematics are still on track to be completed by the end of February. All the FE analogue components are complete and the BE and 8 MByte memories could be completed before the drawing office finishes the FE. However, the drawing office have now said they cannot start layout for yet another month, i.e. the beginning of April. This is the second delay and they are pushing us back by one month per month, which is clearly unacceptable. Paul and Rob will apply pressure to prevent any further delays. Although we are likely to be mainly limited by the lack of progress in the firmware design, we cannot allow the boards to be delayed as debugging the firmware on the actual boards would be very valuable. The drawing office must first input the various required changes to the CMS FED design which have been found during the tests, which should take a few days. They should then review the whole card to find and fix any further problems (but this seems unlikely to happen). FE status: Nothing to report BE status: A public version of the CMS firmware should be available by the end of the week. There may be problems distributing the code as it has various disk area names (including drive letters, etc) hardcoded in. DaveM will wait until after the RAL tutorial before trying to use it. BE trigger status: Matt asked about the VME access, which is A32/D32 and allows block transfer. He released an updated version of the previous trigger logic diagram, incorporating some of the ideas from the last meeting. DAQ status: The CMS groups testing the FED are likely to go with the SBS PCI-VME board rather than the Struck. It makes sense for us to get the same board as the FED VME firmware should be identical and hence will have been tested with this board. They are using XDAQ so again, it makes most sense for us to do the same. Imperial have a NI board for initial tests if needed before we purchase a final PCI-VME board. XDAQ works with this board; it has been by CMS also. Requisitions: UCL will buy a demo board (as above) but otherwise we will make no purchases in this FY; the VME crate already ordered will not arrive before April and with the delays in the drawing office, we are not at the stage of ordering the components for two boards, let alone paying for their fabrication. Paul will contact Ken Peach to alert him to the underspend of our 19k allocated this year. Such a large overallocation is difficult to justify given that we were only granted the funds two months ago and will probably result in some criticism from the PPRP (to whom we need to return in 18 months to get funding for the rest of the project). AOB: Do we want to use a cvs repository to exchange the firmware designs? This is preinstalled but the experience of using it on varied platforms has been difficult. Next meeting: At RAL on Tue 11 Mar for the tutorial in the morning and either the CMS design talks or a regular meeting in the afternoon.