Minutes of CALICE Electronics Phone Meeting, 24/04/03 ===================================================== Present: Adam Baird, Paul Dauncey, Dave Mercer, Martin Postranecky, Matthew Warren, Osman Zorba. Stewart Boogert joined for the discussion on software. Minutes: Paul FED testing status: After the meeting, Rob Halsall supplied the folllowing: VME FPGA; BUS interface 32A/32D + BLT is working. Serial engine under test. SLINK interface next for development. Back End; Main aquisition engine with VME SLINK interface is almost fully simulated/fitted. Serial forwarding engine under test - actually communicating with the FE FPGA currently Analogue; Basic tests of a few analogue electrical & optical inputs has taken place using Chipscope. Detailed electrical testing of all 96 channels is in progress. Detailed Optical testing single channels is about to start (at IC). Power; Some trip sensitivity issues but I expect these to be resolved probably related to filtering. Some initial noise problems on the analogue (probably from dc-dc converters) reported - suspect initial electrical connection method for analogue tests was the source of the problem. We are now using a purpose made analogue electrical input test card which has made the signals much cleaner - more detailed measurements will be made in the next week or so. We will probably make improvements to PSU filtering for CMS - these should discussed with a view to putting them on for CALICE. CALICE board status: Schematics and layout for the module exist. Adam is currently tweaking the tracking, etc, but aims to hand it over to the drawing office this month. The module then needs to be step-and-repeated eight times for the whole board; Adam does not foresee any significant new problems with this procedure. The schematics on the electronics web page are now obselete as the FE FPGA has been significantly modified. There will be a new version this month, i.e. next week, and Adam will send it to Paul to put on the web. Roughly half of the known FED modifications which are needed are in the FE part which we will not use. It would clearly be preferable for the drawing office to do (at least) the back modifications first before splitting the design off for CALICE. However, they may not be flexible in terms of effort to be able to do things in the optimal order. Adam will stay in close contact to be sure all the modifications get done. FE design status: Osman asked about Advantage versions, as Imperial just moved from 5.2 to 5.3. (Note added after the meeting: Rob Halsall says RAL is now using 5.4 and believes this will soon be the Europractise standard.) Osman is also using ModelSim 5.6a and ISE 5.1.03i. He has started on the ADC control sequencer and will tie the three ADC control lines (Address, Convert Start and Read) together inside the FE. He has also hit a problem with the DCM tutorial and will exchange an email with Rob Halsall on this as well as look at the Xilinx web site for hints on using the DCMs. The idea of each output line from the FE implemented simply as the contents of a LUT being clocked out was raised as this had been suggested previously. With a 40 MHz clock, period 25ns, then the 100us required for the complete sequence would need 4000 bits or 0.5 kByte. There are around 100 output lines per FE and so this would mean the total LUT memory needed would be ~50kBytes. The FPGA being used can store around 576kbits = 72kBytes, so this would not be impossible. Both this and the state machine design should be considered. DaveM will look at the BE-FE interface code for the FE. BE design status: DaveM has not yet got the existing BE code, so Rob Halsall should be prompted to send this to him. He would like a complete set of the VHDL code corresponding to the current diagrams. Dave thinks a meeting at RAL to go through this would be useful. As a reminder, Paul said the meeting at RAL on 11 March had decided a fourth VME interrupt would be needed. This would indicate the BE memory was full and so would originate from the BE rather than the BE-trigger logic. Matt has received the FPGA test board but has not had an opportunity to try it yet. He has not yet ordered Chipscope. The UCL Atlas work should ease off after a month and be finished by June. Schedule: Some components have a longish lead time and so should be ordered very soon. Specifically, the FPGAs can have 6-7 week deliveries so these should be ordered now. The BE and VME FPGAs are fixed to be the same as on the CMS board; however there is some flexibility about which component to use for the FE FPGA. Given the uncertainty in the speed and logic needed, it was decided to err on the side of caution and go with a more expensive component, specifically the FG456/XC2V1000 with the fastest speed grade, -6. This will clearly support the 160 MHz FE-BE data communication. It is about 30 pounds more expensive than the next choice (FG456/XC2V500-6) which equals around 500 pounds total for the two prototypes. Either reducing the amount of logic and/or speed grade, when there is more experience with the firmware required, will make the production cheaper. This would mean the prototype and production boards may not be compatible, which was not seen as a major issue. Adam will go ahead and organise the purchase of the components needed for the two prototype boards. The design should go to the drawing office this month and it should then be there for all of May. In June, the PCBs can be fabricated with either a 10 or 15 day turnaround (i.e. two or three weeks) and assembly will be 1 week, which means the prototype boards should be available around the beginning of July. (This therefore still corresponds to the schedule on the electronics web page.) The first half of July will be taken up with basic board tests, including JTAG, but from mid-July onwards, the firmware and software should be ready to start being tested. Specifically, we will try to run with the CMS VME firmware and will start with the CMS BE version (assuming the CALICE modifications don't give any obvious dangers) before trying a modified version. This will allow VME access and basic read/write tests, for which software support will be needed. The FE may be needed later in July. Hence, the PC and VME-PCI boards need to be purchased on this same timescale; the crate itself is already ordered and is expected any day now. Stewart pointed out the DAQ software may have a lot in common with the laserwire project DAQ which he is also involved in. Hence, he would like to contribute to this side of CALICE and will send some information on the laserwire DAQ which can be added to the web. Paul also mentioned a DAQ package called MIDAS, from PSI, which had been suggested for use by us. AOB: DaveM asked if we should put the schedule into Microsoft Project. However, there was little experience of using this and, at least at Imperial, there is only one licence within the group so it is not clear if everyone has assess to it. Next Meeting: Phone meeting on Thursday 22 May, probably starting at 4pm as DaveM (and possibly Paul) will be at SLAC and so this would be 8am there.