Minutes of CALICE Electronics Phone Meeting, 22/05/03 ===================================================== Present: Adam Baird, Paul Dauncey, Dave Price, Matthew Warren, Osman Zorba. Minutes: Paul Matters arising from 24 Apr: Adam had sent Paul a copy of the updated schematics, as requested, but Paul had lost the email. It was resent during the meeting. [Note added after meeting: the schematics are now linked from the CALICE-UK electronics web page.] DaveM has still not received the BE firmware (although Saeed is away for 3-4 weeks). It might be possible to go directly to John Coughlan for this; Paul will investigate. FED status: John Coughlan prepares status reports for the FED group and it would be sensible for us to get copies. They are stored on an unlinked web page; Paul will contact Rob and/or John to get the details. Layout status: The board has been in the drawing office since 14 May although Chris Day was not available immediately. Some issues which have arisen: o) There are not enough BE pins available of the right type (1.5V) to use all 18 data lines of the 8MByte memories. The TTC lines are not usable. Adam suggested reducing the number used to 16 bits, i.e. ignoring the parity checking. This was not thought to be a big problem. o) The LVDS input lines from the backplane J0 and J2 will need termination resistors. This will require shifting components around and so it would be best to keep this to a minimum. Around 20 pairs could be done without too much of a problem but going above this would be more tricky. Paul, Adam and Matt will review the usage of the J0 and J2 connections. Adam is trying to ensure CMS updates all their problem reports so as to generate a list of all the modifications needed. Adam has been in close contact with Julien and Christophe to be sure they are aware of the proposed front-panel interface. A first order pin layout has been agreed, with the only decision at present being on whether for the calibration to use 12 analogue and 1 timing strobe or 1 analogue and 12 timing strobes to select the 12 groups of channels to be pulsed. The latter clearly fits in with our DAC scheme better. The VFE engineers are still considering a patch panel but as they will use the same SCSI connector as the readout board, it is not necessary. Adam has put the information on the internal design reviews and a first draft of a user guide on his web pages. [Note added after the meeting; these are now linked from the CALICE-UK electronics page.] The layout will not be completed by the end of the month, as per the current schedule. Adam aims to slip by one month and finish by the end of June, with fabrication and assembly then taking July. Hence, the date for needing the firmware and software is now early to mid August. The schedule on the CALICE-UK electronics web page has been updated accordingly. The initial hardware tests, in early Aug, will be done by Ivan Church at RAL using JTAG and/or Chipscope. It might be useful for people wanting to learn more about Chipscope to go along to work with him during this period. FE status: Osman attended a Xilinx training course which was very valuable and which emphasised the need to keep occupancy of the FPGA below 80%. RAL are now using Advantage 5.4 and everyone will need to upgrade to this version if they want to remain compatible (which is presumably required). Osman asked about whether the ADC conversion should be done during the send of the previous data or after. The latter would take around 1-2us extra per channel, so increasing the time for all channels from around 50us to 70us. This was not thought a big problem, although if possible, firmware for both should be developed and then any extra noise from the former could be measured. BE status: Matt still has a few weeks of work for Atlas before he will be able to work on CALICE. He has now ordered Chipscope. Matt raised the issue of needing a backplane interface card. The need for such a card depends on the details of the signals coming in and out, in particular the NIM-LVDS conversion card. Paul has thought this was a NIM card but Adam thought it might be a VME board; Paul will investigate. The trigger distribution on the crate will probably be done with 3M-type connectors pressed onto the backplane pins. [Note added after the meeting: Rob sent the following; "I believe the NIM to LVDS converter is a NIM module - 34 channels of LVDS to NIM or vice versa, NIM on the Front Panel(LEMO 00), LVDS (VHDCI SCSI) at the back. We would also need to build a VHDCI SCSI connector cabled to a VME64X J2 connector."] The trigger needs to save various small amount of data per trigger to give time histories of the triggers and activity around the valid trigger. Paul asked if it would straightforward to push the trigger data into the 8MByte memory while waiting for the front-ends to be ready to transmit their data. This would allow the trigger data to also be buffered during a spill without being read out per event. Otherwise, the BE-trigger board would have to be accessed for each event, which could significantly slow down the trigger rate. DAQ status: The crate which was ordered through CMS has had delivery delayed until mid Aug. This will be to CERN so we should assume we will not have it until Sep. Costas Foudas at Imperial has compatible crates which we can borrow before then if needed. The SBS 620 VME-PCI adapter board with 100m of FO cable has been ordered and should arrive in mid Jul; the cost was around 3k. The CMS group are using the Hardware Access Library (HAL) CERN package for VME, which looks well written and documented but does not support VME interrupts (at present). It supports the SBS 620 adapter already. Each VME board needs an ASCII description file for the memory map and we will have to specify this soon. It would be easiest to start from the FED version but this has not been written yet. Some progress has been made on the DAQ software (without a VME front end) and reasonable rates of >10kHz have been achieved for empty events. Next Meeting: Phone meeting on Monday 16 June at 2pm.