Minutes of CALICE Electronics Phone Meeting, 16/06/03
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Present: Adam Baird, Paul Dauncey, Dave Mercer, Dave Price, Matthew Warren

Minutes: Paul


Matters arising: DaveM now has received the BE code from Rob and it
 trying to build and understand it.
 Paul got the URL for John Coughlan's web site but was not able to find
 any frequent status reports on it. He will distribute details separately
 as we have been asked not the put this URL in anything on the web.

Layout status: The drawing office have added termination resistors to
 all the BE-backplane lines which require them and are now adding spares.

 Adam has made a table of the available lines from the BE to both J0 and J2
 which is available at
   http://www.te.rl.ac.uk/esdg/calice/cmsfinalfed/j0.htm
 Of the 7 pairs of lines on J0, only 5 are from the BE, with the other 2
 from the VME FPGA. There are 43 pairs from the BE to J2, but only 37 of
 these are tracked as differential pairs. The trigger is assumed to need
 32 (16i, 16o) for the NIM<-->LVDS path to and from the trigger logic and
 then one per board in the system for distributing the trigger. There will
 be 6 boards for the ECAL and probably 2 for the AHCAL, so this makes a
 minimum of 40 trigger I/O. The trigger and clock also need to be input to
 every board. Assuming the 40 are kept on J2 and the trigger and clock on
 J0, then we are 3 pairs short. Adam will see whether it is straightforward
 to retrack some of the non-differential pairs and a back-of-crate card
 will be the backup. This could be physically made at Imperial or UCL. The
 exact numbers of required trigger lines going out of our system is still
 no better defined.

 So far, the drawing office has only worked on the back part of the board.
 The front module layout is almost complete but some of the details still
 need to be cleared up.

 The board schedule has slipped yet again and will now not be ready before
 at least mid-July to go out for fabrication. This is a minimum of two
 weeks delay on the previous schedule.

 One factor in the future which may cause even more delays is the lack of
 documentation of the corrections needed for the CMS board. Paul will need
 to pressure Rob into ensuring those are done in the near future.


FE status: Osman is away so there was little news, although he wants to
 discuss the FE<-->BE interface when DaveM is on top of the existing code.


BE status: Matt has only just received the programming cable for the UCL
 Xilinx test board today.
 

DAQ: There is some pressure to change to the MIDAS DAQ system, although
 it is not clear what the advantage would be. Paul is going to a meeting
 in DESY in two weeks to discuss this.


Next Meeting: UCL on Thursday 10 July at 2pm.