Minutes of CALICE Electronics Meeting, UCL, 10/07/03 ==================================================== Present: Adam Baird, Paul Dauncey, Dave Mercer, Matt Warren, Osman Zorba Minutes: Paul Readout board status: The FE module layout is 90% complete. The BE has had all the CALICE-specific modifications implemented (i.e. 8 MByte memories, power supplies for these and termination resistors for the J0 and J2 I/O; these should be documented on Adam's web site, linked from the electronics web page). The pin-out of the BE FPGA has had to be changed in doing this. There are now 7 usable pairs on J0 (not 5 as previously reported) and 41 pairs on J2 (with 4 remaining single tracks considered to be not good enough for fast differential signals). The requirement is 32 (16 in, 16 out) for the trigger interface to the NIM<-->LVDS unit, at least 8 output for the trigger distribution to 6 ECAL and 2 HCAL boards and 2 inputs for the trigger and clock, making a total of 42. It was hoped that all the trigger-specific I/O would be able to go through J2 and this would require a minimum of 40 of the 41 available lines, leaving little contingency. However, including the J0 pins gives more headroom and this number was considered sufficient to proceed. The actual pins to be used need to be defined by the third week of Aug, so that the crate can be wired up. The NIM<-->LVDS module is a NIM unit with 34 lemo connections on the front panel and a 68-way SCSI connector (as on the readout board front panel) on the back. It was not clear what the flexibility would be for choosing which signals are NIM-->LVDS and which the other way round, but it seems safe to assume we could have 17 of each. Using all of these would actually take up 34, rather than 32, of the 41 available J2 signal pairs. The cable to connect the module to the backplane of the crate would either have to be custom made or would require a back-of-crate transition board. A very simply version of either of these would be sufficient for the prototype tests, although the final version, particularly of the transition board, could be more complex. Paul will investigate getting the transition board done in-house at Imperial. There is one set of components already available for the NIM<-->LVDS module and so we should be able to get one made within a couple of weeks. Paul had visited DESY the week before and it is clear that to run there, the module will be essential, so it was decided that we should go ahead and get one built. CMS have seen some power supply problems of the FED which (it is hoped) are due to their high power consumption and so should not affect the CALICE version. The drawing office should finish the layout and get the board sent out for fabrication by the end of the month. (In fact, Chris Day is away for three weeks from the beginning of August so there would be yet further delays if it is not done before then.) We should therefore work to the assumption that the two prototype boards would be assembled and back at RAL by the beginning of September. Prototype board testing: Paul showed a rough outline of the detailed schedule for the prototype tests. (A modified version, based on the discussion in the meeting, has been added to the schedule on the electronics web page.) Holiday plans are as follows: Adam - last two weeks of Aug Paul - last week of Aug DaveM - effectively all of Sept Matt - last week of July The crate is expected to arrive at CERN in mid-Aug and will then be sent back to RAL soon afterwards. Wiring up of one-off test cables and/or the backplane then needs to be done; this will be done at RAL by Ivan Church towards the end of Aug. The first thing which will be done when the boards arrive back at RAL is JTAG continuity testing for open/short circuits. This will be done by Ivan Church and should take around one week. The highest priority item to do next is to test out the ADCs. Assuming the FE code is not complete at this stage, then this will be some combination of FE firmware and Chipscope. If the BE is not running and hence is not distributing the board clock, there is a space for a local clock oscillator to be mounted for the FE to run from. The more of these tests which can be done with "semi-final" FE code, the better; this sets mid-Sept as the deadline for a first usable version of the FE firmware. This would not have I/O to the BE implemented (as the BE code is unlikely to be ready) and hence would need to hard-code the configuration constants. As DaveM is away for Sept, then the first usable version of the BE code should be ready for the beginning of Oct. This is therefore when the FE code which does the FE<-->BE data I/O also needs to be ready. The first round of software-level tests, using VME, will be done at RAL but as these progress, it will be more efficient to move to Imperial. In November, assuming the VFE board development is proceeding, the whole system will more to Paris for the VFE tests. FE status and schedule: Osman showed the status of the FE development and an outline schedule to finish the first round of design by mid-Sept. He has concentrated on the sequencer to drive the ADCs so far although he is also thinking about the fine sample-and-hold adjustment implementation. He will need to add understanding and using Chipscope to his "To Do" list; he will try to download this onto the IC demo board, possibly using a PROM to fake up the response of the ADCs. DaveM now has the FE part of the existing CMS FE<-->BE serial I/O firmware. BE status and schedule: DaveM has not yet determined the (if any) missing and/or non-functional pieces of the BE firmware. He has also not seen any VME code at all, either in the BE or the VME FPGA firmware, and is clearly concerned about the VME status on the CMS boards. There is no known VME memory map specification available yet for the CMS board; however, this will need to be defined by the second week of Aug to allow the software development to proceed. DaveM will be meeting with Rob on Monday to go through these issues. BE-trigger status: Matt has been trying out asynchronised logic on the Xilinx test board and sees signal skews of up to 2ns, although he has not excluded a synchronised implementation. The integration issues of the trigger firmware into the rest of the BE are non-trivial, particularly if much of the placement cannot be done automatically. Unfortunately, the overlap between Matt and DaveM's availabilities later in the summer is not ideal, so they should coordinate closely over the next six weeks. The first version of the trigger firmware should aim to be ready together with the first BE code at the beginning of August. Test software: Paul went through a list of potential tests for which software will be needed. It is clear we will also need front panel cables for looping back and so these should be ordered. For the prototype tests, these do not have to be very high spec; DaveM will see if he has some. It would be useful to have eight, one for each connector pair on the front panel. We will also need one for the NIM<-->LVDS module so a total of ten should be sufficient. The SBS 620 VME-PCI module is expected at Imperial within a week and a PC and test VME crate are already available there, so basic VME tests can start as soon as the module arrives. Next meeting: At RAL starting at 1pm on Wed 6 Aug. Adam will circulate the room details closer to the time.