test plan 8 Sept 2003.
PCB status in DO (details below must be confirmed with Chris)
Testing being carried out on the CMS FED has led to more changes on the Calice design with a better -5v switcher being required with improved control circuitry for power on sequencing. These should enter the DO this afternoon (8 Sept 2003).
The move to an improved PCB build has been completed with modifications to all impedance controlled signals.
Connection of all the ADC modules to each other and to the back-end must been carried out.
CMS Front panel LEDs must also be moved to the middle bottom of the pcb.
Complete PCB must be finished, including all 14 layers, power planes must be done to latest clearances, solder paste layers, reference designators, drill drawing, assembly drawing, front panel drawing, and all must be checked by another member of the drawing office before release.
To allow early release assembly drawing and front panel details can be completed when the PCB is being checked.
target pcb release date is now 30 Sept 2003
All problem reports for the CMS FED must also be completed before the pcb can be released (James Salisbury has been informed).
Calice pin configurations
complete pinouts should be published as soon as the netlist has stablised.
test rig @ ICL ?
The test rig should initially be set up using a borrowed 9u ( or CMS FED type crate if it arrives in time).
This should allow:
testing of power supplies and hardware infrastructure (a compact flash card read will also be required).
testing of VME access (and VME processor card)
testing of programming (reprogramming) xilinx chips via JTAG from Compact flash cards.
testing using chip scope (xilinx internal logic analyser).
simulation of the Calice card should be possible with ROM emulation of ADCs in the Delay FPGAs.
testing of part of the trigger logic in the back FPGA should be possible.
Note pinouts on the back FPGA change between the CMS FED and Calice design.
This is not a final solution, but should allow alot of experience to be gained and alot of teething troubles to be tackled before the Calice card arrives.
Calice hardware Testing
Digital - JTAG
This will test all digital signals that are connected to a JTAGable pin. This will give a high coverage on the digital side.
Preperation for JTAG will start as soon as a complete netlist is stable, at least two weeks before the card is due in fully assembled.
All unused JTAGable pins must be included in test.
Analogue - ADCs using chip scope.
The ADC cannot be tested directly with "chip scope" therefore Osman's ADC code will probably be required to interface between the ADC and chip scope to capture data like an oscilloscope.