Minutes of CALICE Electronics Phone Meeting, 11/09/03
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Present: Adam Baird, Paul Dauncey, Matthew Warren, Osman Zorba

Minutes: Paul


Matters arising: Paul contacted Saeed Taghavirad about the VME software
 interface but apparently the VME firmware is being written by Ed Freeman.
 He has not answered so Paul will contact him again and Adam will ask him
 to reply also.

 Adam has found Fujitsu pin-compatible memories to replace the obselete
 ones we had been assuming we would use. Bob Thompson should be told to
 order them asap in case there is a significant lead time.

 Adam has not yet ordered the ten 3m SCSI cables, but should do so soon.


Layout status: Adam summarised the status in his web page at:
    http://www.te.rl.ac.uk/esdg/calice/testplan/index.htm
 They would like to aim to release the PCB for fabrication by Sept 30.
 However, as this is too late and incurs yet another month of delay into
 the project, then Paul said it had to be done two weeks earlier, even if
 it required them to work overtime. Due to the very late status, they will
 need to cut corners, for example they must not wait for all problem reports
 from CMS before proceeding. As the CMS board works to a large extent and
 the CALICE board does not need to last for many years, then we must not
 have yet more delay for minor iterations.

 Adam's web page also suggests setting up a crate with a CMS FED to get
 experience with downloading firmware, etc. This would be useful to learn
 the mechanics of loading the FPGAs and might allow some testing of the
 BE, but the FE differences are so great that it would not be worth the
 effort to try to develop FE code to work on a FED. This requires a loaned
 FED and a crate. There are five FEDs at RAL and one at IC, with another six
 in assembly. Adam has talked to John Coughlan who thinks we could borrow one
 of the five but this needs to be checked with Geoff Hall. [Note added after
 the meeting; Geoff has agreed to this.] The crate status is that CERN have
 the LHC crate order (including one for us) but they are lacking people to
 test them. Geoff told them we needed two urgently (including ours) and that
 they should test these asap. They are expected anytime now. Geoff has also
 ordered 6U conversion kits. It was agreed that the most sensible place to
 base this crate would be at RAL as the expertise and equipment is available
 there and that is where the first tests of the CALICE board will be done.
 However, as it is relatively movable, it would be possible to borrow it
 for short periods (~a week) for intensive tests at a University. Adam
 suggested that it might be worth buying a flash reader if being used outside
 RAL.


BE status: Matt reported that he and DaveM had met at UCL a couple of weeks
 ago. They had suceeded in compiling all the existing BE code. Matt feels
 their understanding of the code is much better now, although there are
 still some gaps and obscure areas (such as the memory block). Matt has been
 tied up with Atlas work for several weeks and this will continue for another
 ~10 days.


FE status: Osman has used the place-and-route successfully and checked the
 trigger delay unit functions on the IC demo board with the DCMs running
 at 160 MHz (i.e. x4 of the clock). He observes a phase difference between
 the incoming and outgoing clock which he doesn't understand. However, it
 should not be a problem for us and may even help with the metastate issue.
 The demo board is not fast enough to support the actual required 320 MHz.

 Osman will use the wishbone protocol for the inter-module communication
 within the FE and he has had a first go at implementing it.


DAQ: Paul reported he has VME memory mapping, block transfer and interrupts
 working on the IC VME teststand.


AOB: Matt raised the issue of the cost of the board assembly, as he had
 heard a high price for the CMS FED of around 5k per board. UCL recently
 had a board with 2 FPGAs on it made which costed 2k. Adam thought the CMS
 price was unlikely and might include NRE. The cost depends on how much of
 the assembly can be automated and the RAL DO should be able to send an
 electronic placement for the parts, which will keep the cost down. Adam
 estimated a ballpark of 2k each for prototypes (2 off) and 1k each for
 production (9 off). This compares with a total budget for each board of
 6.1k (averaged over prototypes and production) with an NRE allocation of 5k
 overall. We have a small amount of headroom as the original budget for cables
 was 150 pounds x 100 cables = 15k as it was assumed we would need them
 custom-made. However, now the VFE-PCB is using the same 68-way SCSI connector,
 then we can use off-the-shelf cables which should be substantially cheaper.
 Also, we now only need around 70 cables (60 plus spares) rather than 100.

 Paul asked about who could go to the Paris meeting on Fri 26 Sep. Osman is
 not available and Matt does not have a passport. It was assumed DaveM will
 not be back at work by then, so only Paul and Adam can go. Matt and Osman
 should prepare some slides if they have something significant to show. It is
 important that we show up and give presentations at Paris as we are so
 critically late that we need to project confidence that the electronics will
 actually be built. Otherwise, there is a danger that they will go for an
 alternative solution and abandon the UK. It is also clear we will have to
 negotiate for a later date than March 2004 for the full system test as we
 cannot possibly make that deadline now.


Next Meeting: RAL on Wednesday 1 October at 1pm.