Minutes of CALICE Electronics Meeting, RAL, 01/10/03 ==================================================== Present: Adam Baird, Paul Dauncey, Rob Halsall, Martin Postranecky, Matt Warren, Osman Zorba Minutes: Paul Matter arising: Paul had still not heard from Ed Freeman about the VME memory interface. Adam had a one page summary of the top level map but this had no details on how to use each location. Fujitsu have withdrawn their quotation for 25 of the 4 MByte memories and will now only quote for 480; we need 22 plus a few spares. As they are 40 pounds each, this is clearly far too expensive. There should be several footprint-compatible alternatives, possibly Samsung? These should be investigated asap. As the order time is likely to be around 8 weeks, they are likely to arrive after the prototypes are assembled and will need to be mounted later by hand. Hardware status: Adam showed some transparencies of various aspects of the prototype status. The list of things to do before the board is sent for fabrication (now scheduled for Fri 10 Oct) included: Item 10: Ordering lists; several passive components are still not in hand Item 11: A DO check by an independent DO member; they will treat this as a high priority Item 12: Design review; Adam will review the DO work and Rob will review Adam's work. These will both take a couple of days and can proceed in parallel. They should therefore take Wed and Thu next week. The latest version of the VFE interface has several changes; an "Address" line (which simply lights an LED) and a "Gain control" have been added along with some card identification. There is only one calibration voltage sent to each VFE PCB, which means the response for a 12-channel cable (one DAC controls all 12 while the other controls nothing) is different from two 6-channel cables (each DAC controls 6 channels). Adam will look into the VFE having two lines, one for each half, although our board would not be modified if this happens (at least at the prototype stage). In addition, there is only one shift register output line. This must be an AND (not an OR) of the separate outputs from the VFE chips and would again make more sense if there were two, one from each half of the VFE PCB. For costs of the boards, Bob Thompson has now spent around 30k on components with around 4k still to buy before the prototypes can be assembled. This covers enough components for the nine production boards too, excepting the production FE Xilinx parts (around 8k total if the same components are used as on the prototypes) and possibly the 8 MByte memories (around 1k total). Unfortunately, FE FPGAs with -4 speed grade were bought for the prototype, despite a previous decision (on 24/04/03) to go with the -6 speed. The costs for NRE are estimated at 750 pounds for each of the fabrication and assembly steps for each of prototype and production. The actual fabrication is estimated at 750/board for prototype and 400/board for production (although the latter is a 4 week turnaround, which may be too long). Assembly is uncertain but is estimated at 3k/board for the prototype and 2.5k/board for production. (For comparison, the CMS FED is estimated to cost 2k/board for assembly). [Note added after the meeting: although stated in the meeting that these included VAT, this is not the case.] A comparison of the original and new costs estimates looks as follows. Original New Prototype (2 boards) NRE 2.5 1.8 Components 8.0 7.8 Fabrication 1.0 1.8 Assembly 4.0 7.0 ==== ==== Subtotal 15.5 18.4 Production (9 boards) NRE 2.5 1.8 Components 36.0 35.2 Fabrication 4.5 4.2 Assembly 13.5 26.4 ==== ==== Subtotal 56.5 67.6 ==== ==== Total 72.0 86.0 The total boards cost is therefore around 14k higher than budgetted for. Luckily, there looks to be a 9k saving in the cables, so we are overbudget but by around 5k. However, this clearly means extra effort from ID cannot be purchased using the cable savings. Adam thinks the 3m cable length may not be appropriate and that we should consider shortening them. He has therefore not yet ordered the ones we agreed on previously. However, with around +/-50cm of travel needed for the ECAL itself relative to our crate, it is not obvious that we can go to shorter cables. Adam has old cables we can use in the interrim. Delivery of cables when we order them is estimated to be 2-3 weeks. The NIM-LVDS unit has not yet been completed. The total cost was originally budgetted at 1k although we may be charged that just for the components; the final cost is not yet known. It would be useful to know the latency through this board; it was guesstimated to be around 10ns. Planning: Paul showed there are three upcoming deadlines, all critical path for the ECAL project as a whole. The first is the VFE test, now scheduled for Jan, immediately after the Christmas break. It is not clear the BE and VME interface for configuration constants will be working on that timescale so alternative methods for setting the timing (and other) constants were discussed. The most basic would be hardcoding the values into the firmware, which requires recompiling to change them (~30 mins). Other ways suggested by Rob would be to use block RAM (writable by Chipscope?), virtual I/O to read/write from disk files or to build an RS232 port into the FPGA firmware and use this to write values. The same solutions would also be possible for reading out the ADC data. Adam suggested putting an RS232 interface chip onto the board but this was rejected as we don't want to change anything in the prototype design at this point. This would be done using a simple external board, or even the Xilinx demo board. Osman will need to do further work on the fine timing adjust needed for these tests, as the -4 speed grade won't support his current design. There are possibilities such as using two 160 MHz clocks, with one inverted so by choosing which to use, an effective 3ns shift can be done. Also, the chip DCMs can run in high frequency or low frequency modes so it was thought a solution would be possible. Osman will be away from Dec 12 to Jan 5, so Rob may need to help finish up the FE code in preparation for these tests. The tests might show too much ADC noise; one possibility would be grounding. The agreed grounding scheme is to have separate power supplies and grounds for the VFE PCB and the readout boards/VME crate. The cable shield and housing will be directly grounded at the VFE end and be connected through a ~100ohm resistor to ground at the readout board end. However, it is not known if the cable housing can be guaranteed not to be shorted to the front panel and hence to the crate at the readout board end. This needs to be investigated urgently before the VFE PCB is finalised. The options are: - Check if cable metal housing is actually connected to the cable shield. (If not, how do we connect the cable shield to ground anywhere?) - Check if there is sufficient panel clearance to guarantee no shorts without removing all the panel metal and hence mechanical strength. - Change the grounding scheme so the shield is grounded at the readout board end and goes through a resistor at the VFE PCB end. This will require them to change the VFE PCB; it would be prudent to alert them to this possibility asap and even suggest putting in this as an option with a short rather than a resistor used if the original scheme will work after all. - Use a plastic front panel or no front panel at all (if mechanically feasible). There was a discussion on how to get trigger signals in for this test to the J0/2 backplane pins. Rob suggested a custom cable which could then connect directly to the NIM-LVDS, although Matt still favours a back-of-crate card. Paul will talk to DaveM to find out his opinion on the upcoming deadlines w.r.t. the BE development. CMS test crate and FED: A 6-slot, 9U test crate and a CMS FED have been set up in the RAL test lab for CALICE use. Rob demonstrated loading firmware to it. Osman, Matt and DaveM should schedule time using this between themselves Next meeting: To be arranged by email