Minutes of CALICE Electronics Meeting, RAL, 23/10/03 ==================================================== Present: Adam Baird, Paul Dauncey, Ed Freeman, Rob Halsall, Martin Postranecky, Matt Warren, Osman Zorba Minutes: Paul Status: The board was sent out for fabrication yesterday to DDI. They have received the board data. This is the first time RAL have used this company and there will be a delay because DDI need to check RAL's credit history. In addition, although we are paying extra for a 10 day turnaround, they cannot yet tell us when the 10 day period starts, due to other work they have. This is obviously worrying. They will be chased up this afternoon after the meeting and a firm start date fixed; Rob will circulate the result of this asap. The company usually used by RAL, Express, have been having problems recently (with the CMS FEDs, amoung others) and in addition would probably not accept the board because of marginal track widths and separations. It seems the order has already been placed with DDI and so could not be withdrawn anyway. [Note added after meeting: DDI should finish the boards and return them to RAL by Thu 6 Nov.] The cost for the 10 day turnaround is around 600 pounds more than for 15 day. The fabrication cost is 1039/board (note, Adam's spreadsheet was not updated for this value), with NRE additionally at 700 for setup and 500 for board testing, all exclusive of VAT. The assembly is now estimated to be 3500/board, with 1200 of NRE, all again exclusive of VAT. The assembly has not yet been booked but should be done as soon as a return date is fixed with DDI. The total costs in kpounds are outlined in the table below Original Last Mtg New Prototype (2 boards) NRE 2.5 1.8 2.8 Components 8.0 7.8 8.1 Fabrication 1.0 1.8 2.4 Assembly 4.0 7.0 8.2 ==== ==== ==== Subtotal 15.5 18.4 21.5 Production (9 boards) NRE 2.5 1.8 2.8 Components 36.0 35.2 36.7 Fabrication 4.5 4.2 4.8 Assembly 13.5 26.4 23.3 ==== ==== ==== Subtotal 56.5 67.6 67.5 ==== ==== ==== Total 72.0 86.0 89.1 so the overall total has increased by around 3k since the last meeting. We are around 6k above budget overall, including the 10k saved from the cables. The NIM<-->LVDS board will now cost 800 plus 1 staff-week of effort (~1200) giving a total of 2000, twice the original estimate. The staff effort was included in the original 1k but now will appear in the (separate) ID effort budget. We will need this board soon, if only to check the trigger latency and jitter through it. Before being submitted, the CERC board was only given a cursory review. Contrary to what was decided previously, Saeed rather than Rob was assigned to review Adam's work but then concentrated mostly on the back end. He did find one error which was fixed before submission. Hence, the front end has not been thoroughly reviewed. One other known problem with the BE is that the DCI resistors are on the wrong pins but if using LVDS (as we are) then this should not be a problem. The D.O. still needs to do the front panels (~100 pounds each to manufacture) and the assembly drawings and so will continue to incur effort costs for some weeks yet. Adam wants to rename a lot of the signal labels on the schematics. As long as a consistent set are produced before the boards are ready for testing and the schematics are updated accordingly, then this can be done. However, the current schematics (with the error found during the review included) should be frozen and released immediately; Adam should send them to Paul asap. Other documentation should be brought up to date while we are waiting for the boards to be manufactured. In particular, the VFE interface, FE I/O lines and J0/J2 I/O pins should all be written up clearly within the next three weeks. The BE memories have been ordered with a 6 week turnaround and so should arrive by the end of Nov. This should be after the boards have been assembled so the memories will be added later; no temporary component will be put on instead. Despite his reservations about the 3m length of the cables at the last meeting, Adam suggested going ahead and ordering all 65 cables immediately. However, as the mechanical structure is still undefined, it is not clear if 3m really is the optimal length. This will become firmed up around six months from now. It was decided to buy ten 3m cables now (as this is the number needed for testing the prototypes) and be prepared to buy another 65 cables (rather than 55) if a different length is needed in future. The cost of the possible extra ten cables would be around 700 pounds. We will order 70 SCSI connectors for the VFE boards as the Orsay people do not seem to be able to find a supplier; we will sort out how they should refund the money later. VME use: Ed reported on the VME interface and the VME FPGA firmware status (see talk). Of his list of things which are not implemented, the only one we would really need would be the interrupts. Paul reported that the HAL software only specified the actual memory locations in one flat file, so changing them should not cause any problems for software. The FE FPGA writeup Ed refers to has a RAL internal web address; the external version is http://www.ins.clrc.ac.uk/esdg/cms-fed/firmware/fe-fpga/docs/fed_fe_fpga.pdf FE firmware: Osman reported on his modifications to the existing firmware designs due to having speed grade -4, not -6 as expected (see talk). Test board: Martin presented his ideas on the test board (see talk). The board could be completely passive, requiring no power cable but needing manual switching to test all analogue channels. Alternatively, there could be active switches controlled by LVDS outputs from the FE FPGA. A commecial cable tester would be around 200 pounds. Schedule: Paul showed the latest version of the schedule (see file). Note, the JTAG testing will be done by Richard Matson, not Ivan Church. There is also no sign of the crate yet, although Paul was told there were two for CMS and the one for CALICE on a lorry at CERN bound for RAL some weeks ago. BE trigger: Matt presented some ideas on the trigger and code organisation (see talk). As Paul had left, his summary of the rest of the meeting is given below. - Rob will finish off the RS232 RX/TX modules and send me the code. - I will build these into a system that allows reading and writing of 32 bit data to 16 bit address space (serial to A16 D32 parallel basically). Osman is happy he can interface to this. - This can be controlled using Python scripts (Rob has written some already), although, a C/C++ version will probably be useful too. - I will borrow/generate a skeleton BE-FPGA that sets up the clocks for the FE-FPGAs and passes data from the back-plane. - A dev-board will be used as the RS232 interface and house trigger functions. These will be fed to the back-plane via a custom connector (Rob to supply part-number). - This will allow Osmans dev-board to talk to Matts dev-board in a test set-up (at IC?) - without a FED/CERC in sight - I will investigate any interfaces required by the French and integrate them into the dev-board Trigger system. - Adam has supplied CERC BE-FPGA pin info. I will ask Ed to supply FED BE pinouts, and combine these into a single list. Next meeting: Thu 6 Nov at RAL, starting at 1pm.