Minutes of CALICE Electronics Meeting, RAL, 06/11/03 ==================================================== Present: Adam Baird, Paul Dauncey, Ed Freeman, Rob Halsall, Dave Mercer, Martin Postranecky, Matt Warren, Osman Zorba Minutes: Paul Last minutes and matters arising: The two prototype CERC boards are now expected to arrive at RAL tomorrow rather than today. They should then be back from assembly by Mon 17 Nov. The NIM-LVDS board will be ready within ~1 week. This then needs to be measured for jitter and latency. The one error caught in the review has been corrected on the schematics and they have been made more readable. The latest version is at http://www.te.rl.ac.uk/esdg/calice/review/idr7/pc3252m1ccts.pdf There was a discussion on whether the naming conventions should be changed. It was thought easier for Matt to maintain an FPGA pin list conversion table than to do the work needed to change the schematics. There is other documentation, as listed in the last meeting, which needs to be written up also. No one has yet been volunteered (assigned) to do this. The 10 cables have not been ordered, due to a problem with cancelling the previous order for all cables which was on a credit card. We may need to scrounge the cables needed for the test period. The cable we will buy is not halogen-free; we would need to buy ~1km of cable to get this rating whereas we only need ~3m x 65 ~ 200m. The crate has finally arrived and is in the test lab at RAL (see below). There is a new web page for weekly Project Monitor Forms at http://www.hep.ph.ic.ac.uk/calice/elecStatusReports/statusReports.html There were some matters arising from the first (only, so far) on 31/10/03. The list of components still needed was; front panels (which are not needed for assembly), power supply capacitors (for which substitutes have been found) and oscillator blocks (which have been borrowed from CMS). The assembly company have requested the stiffener bars (vertically down the centre of the boards) be fitted before assembly, so two are being manufactured. Status: Ed has produced a first version of a FED VME user guide, which is available from the meetings web page. He has also documented the FED FE and BE command lists (designators and data lengths and formats for the commands to these FPGAs) and the VME memory map; again, see the web page. Adam reported that he had been told he may have to stop working on the CERC due to a shortage of RAL effort remaining in the budget. Paul had been told just before the meeting by Ken Peach that five extra staff months which Paul had asked for should be assumed to be available. Paul will need to follow this up, but we should work on the assumption that Adam continues on the project as he is considered essential to the CERC testing over the next few months, as well as for any relayout necessary. Adam will concentrate his effort on the technical issues, leaving the project paperwork etc, to Rob. Planning for test period: Rob showed his overview of the test period between now and the Paris VFE test (see talk and schedule).He would like to do the VFE test in Dec rather than Jan, although is it clear this would be hard to achieve in the time available. The QDRs are now likely to arrive before assembly is completed. Even if not, the two prototype CERCs can have the QDRs assembled afterwards one at a time so there will not be any time when both boards are not available. Paul went though a list of non-CERC items which must also be remembered for the tests. These were: o VME crate: a basic check is needed and the 6U section should be fitted. These can be done at RAL, althought the 6U conversion kit is not there yet. The PCI-VME interface cards will be brought from IC, along with the PC in which the PCI card is installed, at some point in the near future. Details of the network configuration for RAL are needed before moving it. When it is working, a VME check of each slot should be done. o Back-of-crate connections: connectors and cables for the few signals needed for the tests need to be found and wired up. o NIM-LVDS module: a cable to connect this to the back-of-crate is needed. Also, the jitter and latency tests need to be done. Dave pointed out that an XOR CMOS chip used in the design has a large skew but could be bypassed. o Cables: we may not have 10 "final" cables, but we will use what we can get for now. o RS232 and level translator: the RS232 port on the IC PC (using C++) or on the FPGA download PC (using Python) on the test bench could be used. The level translator on the FPGA development board can be used to convert to TTL and/or LVDS. Matt described an RS232 protocol and test module he is developing (see talk). He assumes RS232 with 8 bits, no parity and one stop bit. It was suggested that he keep the address on a short word boundary and the data on a long word boundary. His module could be included in the FE firmware. Alternatively, it could be put in the BE and the FE-BE lines would be used to pipe the serial data to and from the FEs. This would allow the RS232 to be hooked into the back of the crate. For the FE direct method, it could go through any spare pins, such as the link array. Serial commands: Paul had a first list of serial (VME) commands for the CERC. For the record, these are: o Global: Reload firmware (except for VME!) Read monitor data (temperatures, etc) Clock select o BE: Soft reset Clear data (QDRs and any internally stored data) Select active FEs (mask out FEs with no cable) Load configuration data Select BE as trigger BE Clear trigger Load trigger configuration data o FE: Soft reset Select configuration/run mode (prevent configuration updates or not) Load fake event Select data/calibration mode (whether to use DACs or not) Select no/internal loopback (DAC directly into ADC or not) Set DAC value Set VFE calibration group Select VFE module type (full, right-half or left-half) Load timing configuration data Any of these with data or which set a state need to be able to be read back also. The above list assumes most (all?) of the configuration data are loaded as large blocks rather than in small pieces. This was thought easier to implement. Crate inspection: The meeting moved to the test lab, to look at the VME crate. The maximum dimensions are 91cm deep x 44cm wide x 49cm high. The PS covers J1 and partially obscures J0, which will make installing connectors there a bit tricky. The 6U unit is expected soon and can be installed by Ivan Church. Next meeting: Not fixed at the meeting, but was arranged afterwards to be on Thu 20 Nov at RAL, starting at 1pm.