Minutes of CALICE Electronics Meeting, RAL, 20/11/03 ==================================================== Present: Adam Baird, Paul Dauncey, Martin Postranecky, Matt Warren, Osman Zorba Minutes: Paul Matters arising: From last meeting and Project Management Form from 14/11/03. The two assembled CERC prototype boards are now expected at RAL on Fri 21 Nov, which is four days later than originally hoped. Eight cables have been borrowed to use for JTAG and other testing. The QDR memories have, in fact, not arrived in time to be included in the board assembly, so they will have to be added later. The status of the NIM-LVDS board, due last week, is not known. The crate has had a first-order check by Ivan and he is currently fitting the 6U conversion kit, which covers the first four slots. Hardware status: The boards are expected first thing tomorrow. The JTAG tests are complicated because the front panel SCSI cables and missing QDRs require the netlist to be modified by hand. Hence, Adam estimated two days rather than one as the minimum time for these tests, if everything goes well. This gives Tue 25 Nov as the earliest time to try out the FEs (see below). Adam and Richard Matson will do the JTAG tests together. Adam should keep everyone else informed about progress daily so they can plan their travel to RAL. The hot-swap circuitry has been modified from the CMS design and so may not power up immediately. The CMS expert, James Salisbury, is available if there are problems. In the worst case, this can be disabled as it is not needed. The grounding scheme agreed with the VFE is now that the CERC will ground the SCSI cable shield and housing, while the VFE connects them to ground via a 100ohm resistor. Matt will maintain the spreadsheet with the BE pin lists and Osman will do the equivalent for the FE. They need the latest compatible pinuse and netlist files. FE test status: Matt has finalised the RS232 protocol to 8 byte packets and it has been seen to work on the development board. There are two options for using it; directly to the FE or through the backplane and via the BE; both should be tried in case there are problems with one. The FE tests require initially just a clock from the BE; Matt has firmware for this and has tested it on the FED. It is not trivial as it organises the clocks correctly as the BE and subsequently FEs boot up in order. Osman presented the status of his work (see talk). He tried to test several blocks at RAL (shown in green on page 2 of his talk) but failed to get any sense from Chipscope, despite Ed's help. Ed can run Chipscope with one of his designs so it is hoped this is a trivial error somewhere. However, until this is shown to work, it could be a major issue to getting the FE tests going next week. (Ed and Rob are at a Xilinx workshop today so they will try to find out what might be going on.) If Chipscope fails to work, then the fallback is to run "blind". The RS232 link can be tested by writing and reading to the configuration RAM. Signals to the outside of the FPGA can be observed using a real scope, although this requires the real CERC, not a FED. The pink block needs some work before it will interface to Matt's RS232 link, while the ADC and DAC blocks exist but have not been imported yet. The configuration data have been defined to first order by Osman and he has a spreadsheet of the RAM layout (see file). Each FE requires 124 bytes, although he has reserved 4kBytes of address space. The event data (as opposed to configuration data) will also be read via RS232 for the Paris tests. It is stored in the FE in a FIFO and so could be implemented as two addresses, one to read the FIFO and the other to indicate if there are further data to be read. Osman and Matt will sort out an interface. Osman also wants eight command lines to be added to Matt's protocol and this will be done. There are now only three weeks left before Osman leaves; this defines the available time for him to prepare for the Paris tests. Software status: Paul has successfully read both Rob's and Matt's development boards running (different) RS232 protocols using C++ on the IC Linux PC. He will keep the software up-to-date with the future changes to Matt's protocol. He also succeeded in reading the basic VME status words from the FED in the small crate and has read and written to a register from VME using the serial buffer protocol of the FED. One issue is that the PC is connected to the bench power supply and so has its supply cut each evening. Firstly, it does not boot up automatically the next day when the power is restored so that remote access is not possible. Secondly, a hard power-down can cause corruption on the disk. Hence it should be moved to a continuous power supply. List of CERC tests: The list of things which need to be done in the next few weeks are, in time order: 1) Successfully sort out the pin lists such that the FE firmware can be downloaded correctly. 2) Check the basic functions of the ADCs. 3) Measure the ADC noise; Adam expects a couple of LSBs. 4) Apply a DC voltage to the front panel input to measure the dynamic range. 5) Apply an AC voltage to the front panel input to observe a sine wave. 6) Enable the DAC and use internal loopback to measure the ADC response. 7) Use the DAC with an external cable loopback to measure the ADC response. Task 1 requires a UCF file for the FE to be sorted out. This does not yet exist and this could cause a delay if not organised urgently. The initial tests could be done with a minimal file with all unneeded I/O pins set to be tri-stated. Adam should supply the relevant lists (and information to understand and use them) to Osman asap. For the Paris tests, in addition to the above, we will need to have the sample-and-hold fine adjustment in the FE and the trigger distribution and hold-off in the BE. Documentation: The documentation web page http://www.hep.ph.imperial.ac.uk/calice/electronics/electronics.html is very out of date and needs a thorough review and rewrite. The most urgent things are: o The VFE/front panel I/O definition; there were several changes just before the prototype boards were finalised. The most up-to-date version of the VFE SCSI connector schematic was given in Adam's talk on 1/10/03. Paul will try to merge this into the existing document. o The FE I/O definitions; both for forward-going signals (to the ADC, DAC and via the jumper block to the SCSI connector) and for backward-going signals to the BE. Adam and Osman should make up this list. o Backplane I/O. As this will be done in the simplest way for the Paris test, it was concluded that the final usage does not actually yet need to be defined for some months. Next Meeting: RAL, 1pm on Thu 27 Nov. This will be a short meeting focussed on immediate needs so as not to disrupt the ongoing work on the CERCs.