Minutes of CALICE Electronics Meeting, RAL, 27/11/03
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Present: Adam Baird, Paul Dauncey, Ed Freeman, Rob Halsall, Matt Warren,
 Osman Zorba

Minutes: Paul


Matter arising: The NIM-LVDS board should now be ready, but its status is
 still unknown; Rob will follow this up.

 It was confirmed that Matt will maintain the BE pin list and Osman the
 FE pin list.

 The Imperial PC in the test lab, calicepc.te.rl.ac.uk, has had its power
 source moved so it can be on permanently. It is behind the RAL firewall
 and so can only be accessed from other computers within RAL.


Hardware status: The two CERC boards arrived on Fri 21 Nov. Both have passed
 their JTAG tests. Known problems seen so far are:
 o The hot-swap power circuitry has wrong RC timings and so does not power
   up from cold reliably. Pressing the reset button seems to work. James
   Salisbury will look into this.
 o There are no QDRs and they are now expected early Jan. These are not
   needed for the VFE test, but will be useful for VME tests later.
 o Two capacitors were assembled in place of resistors on one of the CERCs;
   this was just an assembly error. Adam has already removed them.
 o There are no oscillator blocks on the boards, but these are in hand and
   can be put on straight away.
 Once the oscillator blocks are mounted, the boards will be ready to start
 testing in the crate.

 Adam has recived an email from Julien Fleury saying they will assemble
 two VFE PCBs with four VFE chips on each around Dec 15. It is not clear if
 this date is the start or end of the assembly. The email suggests they
 may allow us to borrow a board to try in the UK, although it is a little
 ambiguous on this. Issues of power supplies would also need to be settled.
 In any case, to do the final VFE test with cosmics, we will need to use the
 cosmic test stand in Ecole Polytechnique, so we would still need to plan to
 go to Paris, albeit later, even if we get a VFE board in the UK. Adam will
 forward Julien's email to Paul.

 We do not yet have the 10-way and 5-way combined jumpers for the link arrays
 although they have been ordered. At present, the CERCs are linked for the
 all-digitial version, so there should be no need to move the jumpers until we
 start testing through the front panel. A SCSI connector with a short cable
 with exposed ends would be useful for these tests; Adam or Rob will try to
 find one. There is an analogue scope on the test bench already.

 A reminder; always use the grounding wriststrap when touching the boards.


BE/RS232 status: The RS232 serial I/O code can now read and write to block
 RAMs on the development board and the BE but not yet the FEs.

 A separate firmware code has tested clock distribution to the BE on the
 FED, but this has not been merged with the serial I/O code yet.

 The BE will also need trigger input, fanout, latch and latch reset code
 for the VFE tests.

 The serial I/O, clock and trigger distribution code for the FEs will need
 to be merged with Osman's code. This may be tricky to organise sensibly as
 some parts, such as the FIFOs, are still missing. At least the interface
 definition should be frozen asap.


FE status: The Chipscope/VIO problems have been resolved in so far as they
 now work, but it wasn't clear what was the cause of the previous problem.
 It is reproducible, but could be something like the DCM locking or the
 reset chain.

 Osman needs to set up his new RAL computer account correctly before
 proceeding further. He will come to RAL next Monday and stay for the whole
 week. He will need to be able to backup his work; Matt recommends using
 Unison (which runs rsync) but it is not known if this is available at RAL.

 The plan for the FE tests is in the following order:
 o DAC; enter values through Chipscope and see the output on the scope or DVM.
 o ADC; sequence the ADC readout for just one component initially.
 o Loopback the DAC into the ADC and check the reading change as expected.
 o Duplicate the code to multiple ADCs.
 It was thought that the RS232 interface should be got working before going
 to a "dynamic" level of testing with varying DAC values or sine wave input.

 The FE needs to add an event (i.e. ADC) data FIFO for readout to the BE.
 Osman already has inplemented this, but it needs to be connected into Matt's
 serial I/O. 

 Adam suggested letting the ADC sample continuously and then simply dumping
 out the data to disk through VIO as bandwidth becomes available. Adam should
 be available for helping Osman all next week.

 Ed will help Osman make a flash card when the BE and FE designs have
 stabilised a little. The VME firmware is loaded from a PROM, not the
 flash card, and this should also be programmed so that the VME code, and
 hence clock distribution, is always available.


Software status: The software can handle the latest features of the serial
 I/O interface.

 Paul has written a CERC emulator which uses the second RS232 port and a
 loopback cable from the first port to respond to the serial I/O commands.
 This allows the software to be tested when the CERC is not usable.

 Paul has not yet been able to work on the FED VME data path, i.e. the VLink,
 as he has not figured out how to trigger the board to create the event data.

 We may need to return the FED soon, so it would be useful to do as many of
 the VME tests as possible on it before then.


Next Meeting: RAL, 2pm on Tue 9 Dec; note later time.