Minutes of CALICE Electronics Meeting, RAL, 09/12/03
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Present: Paul Dauncey, Ed Freeman, Rob Halsall, Dave Mercer, Osman Zorba

Minutes: Paul

Last minutes and matters arising: The expected arrival date for QDRs was
 not known to anyone in the meeting. CMS have experience with taking off QDRs
 and replacing them successfully (due to a problem with the power-up sequence).

 The NIM-LVDS module has been delivered but has not been checked at RAL yet.

 It was not known when the 5- and 10-way jumpers would arrive.

 The number and cost of the SCSI connectors sent to the French groups was not
 known; Paul will need to know the cost to arrange some level of repayment.

 There was some confusion about whether the one known modification (which
 prevented the VME FPGA from loading correctly and was fixed by a single
 wire on each board) was the same problem as the power-up sequence failure.
 As at least CERC SN002 still requires a reset by hand after power-up
 most of the time, it was thought most likely that the power-up problem was
 separate and had not been fixed. ROb will check the report cards.


Hardware status: In Adam's absence, the status was not known.

 We will need CompactFlash cards for the firmware to boot from on power-up,
 so 11 should be ordered (delivery time unknown), size 128MBytes, at a cost
 of around 20 pounds each.

 As discussed previously, we will need a SCSI connector with a short section
 of cable with bared ends for testing; RAL said they could provide this.


FE status: Osman showed some slides of his work (see talk). He can now
 reliably load the DAC using Chipscope. He can also sequence the data out
 of the ADCs, but sees some odd behaviour. Specifically, one of the 12 ADC
 channels, SDB_5, seems to send its data a few clock ticks early; this is
 not understood. Also, only a particular range of DAC values gives sensible
 (i.e. stable) ADC output values; going below around 1V seems to cause
 problems. In addition, he sees markedly different behaviour using the DAC
 looped back internally compared with sending out to the front panel and
 then looping back with wire.

 The status of the VFE production in France is that they now have 3 VFE
 PCBs. They will partially populate two by ~Dec 15 and test these, adding
 a single Si wafer if things look functional. Only at the end of Jan will
 they fully populate a complete VFE PCB with 12 FLC_PHY chips and six Si
 wafers. We need to do our final VFE tests with the fully populated board
 and so it is likely we will have a week or so after the Christmas break
 before going to Paris.

 Hence, the conclusion was that Osman should spend the rest of today
 investigating the ADC problems and then the rest of the time before he
 leaves at midday on Thu 11 Dec interfacing his DAC and ADC I/O to Matt's
 RS232 interface.


BE status: Matt had sent a diagram of the serial interface data and trigger
 flow (see file) which was discussed. Two items were raised. Firstly, the
 loopback on the trigger latch was not understood and it seemed the latch
 would be synchronous and hence would round the trigger to a 40MHz clock.
 Secondly, the possibility of a FE "broadcast" (i.e. simultaneous signal
 to all 8 FEs at once) was thought useful, although it would be difficult
 to implement because of handling the reply. Paul will raise these issues
 with Matt.


Software status: Paul has been using the FED S/N 004 (which has now been
 removed to have opto-receivers installed) for checking software. It has just
 had its PROM (for VME) and CompactFlash (for BE and FE) upgraded to the
 latest firmware versions, namely
     VME  0x11000304
     BE   0x1200022c
     FE   0x1300030d (although this reads in software as ...20d)
 These have cured several of the odd features Paul had seen previously.

 Paul has not yet tackled the I2C interface to the LM82 temperature sensor.
 He asked for documentation on this.

 Paul listed several commands which will need to be performed at high speed
 (up to ~2kHz) during a run, depending on the readout mode. These are
   Check for the trigger latch being set (BE-trg, one CERC only)
   Check for the spill status (BE-trg, one CERC only)
   Check for the QDR (nearly) full state (all CERCs)
   Get the number of events in the QDR (all CERCs)
   Reset the trigger latch (BE-trg, one CERC only)
 None of these are (currently) foreseen to be available directly via VME
 so that they wil all need to be accessed via the serial I/O protocol. Paul
 has seen a rate of around 5kHz for small serial I/O commands, which might
 be sufficient if the above information can be extracted in combined
 packets, rather than separate ones. This will require careful planning of
 the serial I/O interface. The alternative would be to add status lines
 directly to the VME FPGA and have them appear as an extra status word.
 By multiplexing, it would be straightforward to put 32 bits of status
 into one of two lines. However, there are only 4 VME-BE lines which are
 not already reserved by CMS, so this should not be done unless the serial
 I/O solution is proven not to work. The same holds for interrupts, which
 would be an alternative to polling for the trigger latch and spill status.

 Paul has a preliminary list of commands (expanded from the list given in
 the minutes of the 06/11/03 meeting) which may be needed (see file).
 

Next meeting: Fixed afterwards; Mon 12 Jan, 1pm at RAL.