Minutes of CALICE Electronics Meeting, RAL, 12/01/04 ==================================================== Present: Adam Baird, Paul Dauncey, Ed Freeman, Matt Warren Minutes: Paul Matters arising: Since the last meeting, there have also been two project monitoring forms. From all these: o Adam has only sent a few SCSI connectors to LAL for the VFE boards. He is not planning to buy enough for all 60 of their boards so there is no issue of repayment. o The power-up problem seen during the JTAG tests (but not in the VME crate) has not been studied by James Salisbury yet. It makes most sense to have representative firmware first to get a reasonable power load before this is further diagnosed. o In Rob's absence, it was not known if the 11 CompactFlash cards had been ordered. It was also thought sensible to order a CF reader/writer as well. o We will need a SCSI cable with bare ends; Adam has a cable which can be chopped when needed. o The QDRs have not arrived and no delivery date is known. o The NIM-LVDS unit has still not been tested at RAL. Hardware status: Adam reported that so far nothing had been found which could not be worked around for the VFE tests. The outstanding issues are: o The FPGAs do not boot reliably. After a reset, the FPGAs do not load whereas if the CompactFlash card is removed and replaced, they do. Power up is not always reliable either, but varies; sometimes individual FPGAs fail to boot. This was thought to probably not be related to the power-up sequence problems. o The DAC does not cover the full range of the ADCs. The DAC op-amp drives a fully differential output, but the DAC range only drives this through one half of its range, e.g. the top line of the pair goes from 0 - 2.5V, not -2.5 - 2.5V. This means the ADC will only give output for the top half of its range and this will be true when using the DAC whether in internal loopback or when pulsing the VFEs. The ADC is thought to work in twos-complement (although the data sheet should be checked) so the lowest value is 0x8000 (= -32768) which then rises to 0xffff (= -1) goes to 0x0 (= 0) and continues up to 0x7fff (= +32767). Hence, with the DAC, only values from ~0 to 32767 will be seen (which explains some of the confusion from the initial readings). This raises the issue of both the VFE differential range and where the pedestal is expected to be. Adam will check these issues with Julien as a matter of urgency; if the VFE works like the DAC, then it would halve our useful ADC range and hence resolution. The test of putting a differential voltage into the front panel to check how the ADC responds, see the saturation levels, etc, has not yet been done. This should be done as soon as the ADCs can be reliably read out and should be followed by the sine wave test. Firmware status; Osman was not present but it was thought he had made little progress in the previous week due to the Xilinx software licences expiring. Matt reported he had a few niggly problems with the serial I/O but it was mainly working OK. The external trigger from the development board to the backplane and then to the BE was not yet working. He also sees the FE clocks die when he resets the FEs, at least on one board. His code is at the level where it needs to be merged with Osman's. Dave was not present, but Matt met with him just before the break. He has the latest versions of all the code but could not compile them, probably due to different versions of the Xilinx software. Paul had suggested the first thing he should try is to load the FED BE version will all I/O except to the VME FPGA tri-stated to see if any of the serial commands, e.g. the BE firmware id read, will work. Software status: Paul has got basic LM82 commands working on the FED. He askad about monitoring the CERC on-board power supplies; there is an I2C interface from them to the VME FPGA, but the VME firmware to use it has not been implemented yet. The FED memory map is undergoing a change but this should not be a big problem as it only appears in one ASCII file. Paris organisation: A schedule was sent round by Jean-Charles Vanel (see file on web). The VFE boards did not come back before the break so there will be an extra ~1 week delay to the schedule shown. We should therefore expect VFE PCB A, with no wafers, to arrive in the UK around Mon 19 Jan. We should aim to test this for 2-3 weeks and then move out to Paris around the end of the month, where we can start to look at VFE PCB B which will have one wafer. Later in Feb, VFE PCB C, which will be fully populated, should become available for testing. The VFE was thought to only need +/-5V power supplies so it should be straightforward to run PCB A in the UK; RAL should have spare supplies available for the few weeks of tests. Alternatively, the power could be picked off the crate. It would be useful to get a power connector for the VFE from France along with the PCB. There should be no special mechanical requirements. Paul will ask about this and other items we might need to take out with us. Jean-Charles needs information in advance for people planning on going to Paris in Feb so he can arrange authorisation to get in and out of Ecole Polytechnique. The list of details he needs is 1: Name,first name 2: Current Nationality 3: Date and birthplace 4: Category and number of the passport - authority having delivered it 5: Usual residence (country - city - street - number) 6: Address in France 7: Profession or rank 8: Employer - corporate name - addresses 9: Date of arrival in France (year - duration - object) Please let Paul know this informationb asap if you might be going out for the VFE tests. Adam would be able to go out for around a week as necessary. Matt would be available for most of Feb (excluding the weekend of 7/8 Feb). Paul is very limited for travel during term time and so could only go for the odd day or so. For software people, we will need to rely on Dan Bowerman and the new student Catherine Fry; they will both need to get up to speed over the next few weeks. Paul mentioned about transport and shipping. The easiest way to take the equipment out would be in the boot of a car which is taken on Le Shuttle. However, it was not clear if insurance would cover the equipment. Also, it was not known how much paperwork would be needed, even within the EU. Matt knows someone who often drives equipment to DESY and will enquire. Location of tests: When the main focus of testing moves to become firmware development, it would be more convenient to move the crate and boards to Imperial. Adam thought the hardware could be considered as tested when the sine wave test had been done on all channels. It was not clear that would be achieved before the VFE PCB A arrived, although it should be our aim. There was agreement that it would not be good to have one CERC at RAL and one at Imperial as cross-testing between the two helps eliminate one-off problems from systematic ones. Next Meeting: Phone meeting on Mon 19 Jan at 2pm. Rob will try to set up his phone to allow us to call his office number; Paul will connect him with Nigel Watson who arranges conference calls in this way from his RAL/PPD phone for CALICE.