Minutes of CALICE Electronics Phone Meeting, 11/02/04 ===================================================== Present at RAL: Adam Baird, Steve Quinton Present at Imperial: Paul Dauncey, Osman Zorba Present at Manchester: Dave Mercer Present at UCL: Matt Warren Minutes: Paul Matters arising: From the last meeting and PMF dated 06/02/04. Rob Halsall is on leave for two months (until the end of March) so Steve Quinton has temporarily taken over his role during this period. The QDRs, CompactFlash cards and CF reader have been delivered to RAL. Next time there is an update of the firmware on the cards, we should swap to using the new cards and return the two borrowed CF cards to CMS. The cost of these items was not known. The VFE card arrived from Paris; there seem to be enough connectors included for us to use it. The project specification document was not completed by Rob before leaving. It is not clear we have access to all the relevant CMS web pages; some material is on the private pages which require direct URL access. Hardware status: There was no progress on the CERCs as Adam had been working on other projects. Adam has looked at the VFE board. There are only 4 VFE chips (out of maximum of 12) mounted as they only have a limited number and wanted to fully populate another VFE PCB which has silicon wafers. These chips are in positions 1,2,11 and 12, although Julien reported that the chip in position 12 might be dead. There may be other bad channels, although it is hoped these problems are not in the multiplexer chain or they may prevent readout. There is no SROUT signal (the multiplexer output indicating successful completion of the multiplexer chain) on the connector but we can probably pick it off the chip pin to put on a scope to check for it. Adam has checked the board takes power but the possible tests are very limited without the FE driving signals. FE status: Osman showed a few slides on his status. The design is currently 70% full in the FE FPGAs. If he merges the ADC control from all independent to all controlled in parallel, then this is reduced to 50%, obviously at some reduced flexibility. He is currently unable to get the DCM to work in his latest design; the clock LED just stays on continuously. There is no other indication that the design has errors (place-and-route was OK, JTAG load was OK) and the previous version worked OK also, so it is unlikely the CERC is at fault. He will try the design in several FEs on both boards in any case when he goes to RAL tomorrow. If he canot fix this problem, one possibility would be to back off to the version he had in Dec, before the Xmas break. However, Matt had problems using this at the time (although these problems are now understood). It would also not necessarily be useful to find the error as the DCM part of the design should be identical for the two. This work is clearly essential for the VFE PCB test and hence preparations for Paris and so should take priority over anything else. BE status: Dave is now back at work full time. He is still struggling with errors in using the CMS code and so needs to get all versions, directory locations, etc, clear with Saeed Taghavirad asap. He will arrange a meeting with Saeed at RAL as soon as Saeed is available. Adam will check the latest versions of the software used at RAL by the CMS people and distribute them so we can be sure everything is compatible. We also need to check what are the latest firmware design versions in use by CMS. Dave will need software support from Paul and Dan Bowerman to test the VME interface to the BE when he is able to load the design. He should keep in contact to let them know when they might be needed. He should also coordinate with Osman about using the CERCs at RAL. In principle, they can work in parallel, except that Osman cannot use the RS232 connection (which goes via the BE) when Dave is testing his design. Matt reported that he may have some updates for the BE trigger design which can be included at some later date. He should also be able to update the FE block without disrupting Osman's design as long at the interface is kept fixed. UCL have some parts to provide a NIM interface on the backplane. We also have the NIM-LVDS module (which has still not been tested at RAL). To use this, we will need a cable made up with a 68-way SCSI connector and some of the lines wired into the backplane small push-fit connectors. RAL had previously said they would provide such a cable. Xilinx order: Adam has found out that Xilinx are currently quoting a 15 week delivery time. It is not clear if this is really realistic. If true, it means we should be ordering the final FPGAs asap. The previous assumption had been that the BE should be kept identical to CMS (so as to be sure the code would fit, although we have the extra trigger code, which should be small). However, the FE code is still not finalised enough to know if we have to go to a larger (i.e. more expensive) version. Osman's current design takes 50-70%, which includes the RS232 interface but does not include the final BE-interface. This latter should be close to the CMS design so Paul will try to find out how much that occupies in the CMS FE design. Osman's numbers presumably exclude using a smaller FE FPGA component. Equipment moves: The plan is still that the crate will stay at RAL until the sine wave test has been done on all ADC channels. It will then come to IC until the firmware is developed enough for the Paris tests (and/or they are ready for us to come out). It then gets shipped to Paris. However, we have been asked to change location at RAL to the neighbouring room. Given that it does not look like the crate will be coming to IC within a day or so, it seems we should do this move at RAL immediately, preferably before Osman arrives tomorrow. Next meeting: Phone meeting at 2pm on Thu 19 Feb. Call Rob's office, i.e. 01235 445140 as before.