Minutes of CALICE Electronics Meeting, Imperial, 18/03/04 ========================================================= Present: Dan Bowerman, Paul Dauncey, Catherine Fry, Matt Warren, Osman Zorba Phone from RAL: Adam Baird Minutes: Paul Matters arising: Paul contacted Ed Freeman about the old VME firmware version we are using but this design has been taken over by Saeed, so Ed has forwarded on the query; there is no reply yet. Adam replied to Jean-Charles Vanel that the 0V differential option was OK for us. Adam needs to send his passport, etc, details to Paul asap. Osman has had a look at the NIM-LVDS module (see below). The system manager at Imperial is away, so there is no progress on an electronic log book. However, there is an old-fashioned paper book now with the equipment which should be used. Hardware status: There is no progress on the SER001 failure. James Salisbury needs to look at it to see whether this is related to the power-up issue or not. He may be able to do this in the week; this is clearly urgent for us as we need both boards functioning to go to Paris. Although Adam is confident about the cause of the DAC gain mismatch, this has not been checked yet. The list of known CERC problems (in addition to ones reported on the web problem reports page) is: o Unreliable power up on both boards - needs further investigation. o SER001 (clock?) failure a short time after boot-up - needs further investigation. o DAC half gain range - needs further investigation. FE status; Osman showed some slides of his progress. He measures a NIM-LVDS delay of 28ns, which includes ~4ns of cable delay. The module can also use TTL if the internal jumpers are set correctly. He has solved the issue with the Advantage licence temporarily by accessing the licence server over the network remotely from a laptop. Matt said his dongle could be made available if Osman hits a big problem in going to Paris. The next version of the firmware will have a version number readable at reg_en(49). It will also have a reordered ADC readout sequence, so the order of words in the FIFO is the same as the OUTPUT numbering on the front panel connector. These new features will need to be checked. Osman is getting a small board made to make the external DAC-ADC loopback test easier. Adam predicts the same half gain as for the internal loopback will be seen there also. The extra words seen in the FIFO have been found to be due to the FE running through the DAQ sequence when user read commands are sent. The amount of date is larger because this command is broadcast, but the fundamental effect should not be occurring in the first place. It varies depending on FE; FE4 and FE6 seem to suffer less even though running the same code, so this implies a timing issue or similar. As mentioned in the last meeting, the SROUT requires an extra multiplex clock tick to be turned off after the full sequence, i.e. 19 not 18 clocks in the final system. At present, this will generate another ADC convert cycle and hence a spurious extra word in the FIFO. The FE firmware could generate the extra clock and not fill the FIFO, or could issue a second RESET after the readout sequence. How the SROUT will be detected in the final sytem was also discussed. Two possibilities are to count clocks to see when the rising edge appears and save this value in the FIFO, or to indicate it as high or low at the time of the convert end using bit 21 in each FIFO word. In this latter scheme, all FIFO words should have the bit not set except the last. This second possibility was thought easy to implement and it was agreed to be the one to use. Matt reported the next FE RS232 version will have the trigger synchronised (only) for the counters so they should catch asynchronous triggers and now work reliably. In addition, it should have the user command broadcast fixed. We need spare SCSI cables to go to Paris. Adam had eight for the initial JTAG tests, of which four were borrowed. Of the other four, there is one at Imperial and one at RAL. He will locate the other two and send at least one to Imperial along with SER001 when it is fixed. These cables are all only 1m; Adam will try to borrow some longer ones also. The list of known FE problems is: o ADC BUSY on for first sample - not understood. o Noise on HOLD line - needs further investigation. o VFE type and link array information readback - needs to be implemented. o Extra FIFO data due to user read commands - needs further investigation. o Broadcast user read commands - may be fixed in next version. o VFE chip readout order - may be fixed in next version. o Detection of SROUT - needs to be implemented. o Extra clock or RESET for SROUT - needs to be decided. BE status: Osman reported that he had measured the latency for triggers from the Dev Board to the front panel (temporary) trigger output. He sees this as 32ns including the cables and FE delay. The trigger to HOLD (at minimum delay) has been previously measured to be another 18ns. Matt thinks that of this 32ns the BE contributes 16ns, so few savings look possible. Some jitter was seen between the Dev Board trigger and the hold and this needs to be measured. There is only one trigger input through the backplane implemented in the current BE version, although more could easily be added if necessary, with the trigger being an OR (configurable) of these inputs. The next version of the Dev Board firmware (V5) has the trigger stretched from 40ns to 90ns. It also has a trigger counter. Like the FE, the next BE firmware version will have the external asynchronous trigger synchronised (only) for the counters so they should now work reliably. Matt will add version numbers to both the Dev Board and BE in future. The list of known BE problems is: o Trigger jitter - needs further investigation. o External trigger reliability - may be fixed in next version. Data analysis: Catherine showed some plots of the response to a fixed DAC value of 1000, while varying the HOLD delay and enable bits. Several channels have unexpected shapes, but some show a nice CR-RC shape although delayed by several 100's of ns beyond the TCALIB pulse time. There is a worry that the VFE is not interpreting the CERC signals as expected. This is not understood and needs further investigation. Dan (in plots 4) showed the effect of varying the DAC value for a fixed hold of 32 counts, i.e. 200ns. These are not consistent with Catherine's plots, but were done with all enables on at once so there may be some effect there. In plots 1, he showed residuals from the internal DAC loopback data fitted to straight lines. There are systematic patterns on several channels, but only at the few counts level and there is no sign of a systematic higher polynominal term. In plots 2 and 3, he showed the results of further fits to the sawtooth waveform data. VFE tests: The latest from Jean-Charles Vanel is that they would be ready for us to come out in the week starting April 5. This is getting very close to Easter and so it would be much preferable to go out a week earlier, if only to get set up and continue our own tests. Paul could not go on either Mon 5 Apr or Tue 6 Apr and the Wednesday that week is possibly the last working day before Easter. Paul will ask if we could come out around Wed 31 Mar. AOB: The current version of the CompactFlash card used at Imperial is V3.2. Next meeting: Phone meeting on Thu 25 Mar at 1pm. Call Rob's office on 01235 445140 as before.