Minutes of CALICE Electronics Phone Meeting, 25/03/04 ===================================================== Present at Guildford: Paul Dauncey Present at Imperial: Catherine Fry, Osman Zorba Present at Manchester: Dave Mercer Present at RAL: Adam Baird Present at UCL: Matt Warren Minutes: Paul Matter arising: There is no news on the compatibility of the old VME version we are currently using with the BE version Dave is working from. Paul will chase this up with Saeed. If Adam intends to go to Paris for more than a day or so, he will need to send his passport details to Paul. The Ecole Polytechnique site has relatively high security and these passes are needed even to get in and out of the buildings. The current plan is that Paul will take the equipment out to Paris next week on Wed 31 March. Hardware status: Adam has been working through several possible causes of the problem with SER001, so far without finding an error. The board now consistently stops running about 4 seconds after boot-up. The PROMs we are using should be OK, according to the Xilinx spec. Adam has not yet seen if the clock from the VME FPGA is present after failure or not, although its LEDs continue to flash, implying it is still alive. Adam has observed that the BE clock LED always is off after the board stops, implying it is not just a random halt time. This might indicate a loss of the DCM lock. In case there is a timing edge problem in the BE clock reception, Matt will try to change the BE design to improve the reliability of this code. Adam needs to check any new design using a CompactFlash card and if doing this, he should try it out with the latest FE at the same time. Osman will send Matt his latest FE version and Matt will make a single file of the BE and FE which can be downloaded to a CompactFlash card by Adam. Paul will collect SER001 on Mon 29 Mar in the afternoon, so if at all possible, these tests should be done before then. Adam raised the issue of slowing down the SystemAce load clock; it was not clear if this speed can be controlled by parameters on the CompactFlash card or not. Matt asked whether using a pod connected when booting (on another board) from a PROM might cause problems. Adam said he had got this to work reliably on another project. Adam has also been updating the problem reports on his web page. He has noticed the I2C clock and data lines for the FE FPGAs need to have internal pullups. The BE I2C section is unchanged from the CMS version, so whatever they use in the BE should be OK for us also. We have no way to access the I2C (e.g. the LM82 temperature sensors) yet. The firmware for this is in the BE and the BE-FE interface part of the FE, neither of which is loaded. Adam has also checked the DAC gain factor of 1/2 is as he suspected, i.e. due to the op-amps. He believes the external DAC loopback tests should show effectively the same response in terms of ADC counts per DAC count as the internal loopback. Jean-Charles has said limited space at EP may mean 1m cables are not long enough. Adam will try to borrow at least one longer cable, although it might be 10m, which could introduce noise and another ~40ns of latency. We will clearly take all cables we have available to Paris. FE status: Osman has a new version of the FE firmware which needs to be tested. It has the following new features o The firmware version number can be read from word 49 (address 4*49=196). For the latest version, it should read as 33947654 = 0x02060006. o The ADC data are reordered to agree with the connector OUTPUT order. o The spurious data appear not to be written into the FIFO on userCommands. This presumably implies the timing sequence is not running during this command any more. This has been loaded onto CompactFlash V3.3, with the same BE as V3.2. The ADC BUSY line is still recorded as high for the first sample in each ADC, even though Chipscope shows this is not actually the case. Osman will continue to look into this. Osman has made a simple board for the external DAC loopback tests. By reversing the ADC polarity, we should be able to measure the negative range of the ADCs also. The CompactFlash cards have to be carefully formatted; they are sensitive to the Windows OS used and only Windows98 seems to work reliably. Dave says this is discussed on the Xilinx answer database, number 14456. Osman will format all the remaining CompactFlashes to be taken to Paris. Then, all that is required is copying on the latest file. It is hoped that the Paris tests will include the VFE PCB V3, which has the SROUT coming back to the CERC over the cable. Hence, Osman will implement recording the SROUT state, like the ADC BUSY, in the upper part of the ADC word. Adam has the information on which SCSI pins this will be on and will forward this to Osman. If there is a conflict with the temporary trigger output on the SCSI connector, Osman will reroute the trigger to another spare pair of pins as it has proved useful. The VFE type is supposed to be readable from word 47, although this gives a variable number for the FE with the VFE attached. Osman needs code to read this so as to diagnose further. The link array identification read has not yet been implemented. BE status: There was a new version installed last week, which appears at first go to have fixed the missing external triggers issue. DevBoard status: The latest version of the DevBoard firmware, V6, has now allowed some of the external inputs to be activated. Two appear to now be on when not connected; Matt will fix this in the next version. An external trigger from NIM, via the NIM-LVDS module, to a DevBoard LVDS input was sucessfully seen to count triggers this morning. The latency for this full path has not yet been measured. The trigger jitter for triggers from the DevBoard to the HOLD has been checked and is around 6ns, which is consistent with the rounding of the HOLD to the 160MHz clock, as expected. Jean-Charles has sent a diagram of the trigger setup at EP (see slide) which shows the output is NIM. The DevBoard has no inputs which can take NIM directly so that the NIM-LVDS module will be needed. The EP latency is given as 80+/-5ns. The estimate for our system is 32ns through the NIM-LVDS board, 32ns from the DevBoard to the FE, and 18ns from the FE to the VFE HOLD; a total of 82ns. Added to the EP number, this gives 162ns which is very tight for a 180ns peaking time, particularly if we use the 10m SCSI cables. Paul has asked Jean-Charles if it is possible to use the cosmic discriminator output directly, which is ~40ns shorter in latency. However, he has not yet replied. There is also an issue with using the USB port to communicate with their equipment; we have no code to do this. Data analysis: Catherine showed some plots (see talk 1) of the pedestal and noise variation as the ADC convert start is delayed relative to the multiplex clock. There is no systematic effect on either over the whole delay range. However, the noise seen was around 3 counts, not the ~20 counts seen previously, so there may be a problem with the measurements. This needs to be checked. Catherine has also looked at the DAC response for variable VFE enables and HOLD delays (see talk 2). In all cases, the ADC means are completely independent of the DAC value. In addition, there are several different shapes and timings for various channels. These will probably have to be sorted out with Julien at EP next week. Paris effort: The schedule is still in flux, but the current plan is that Paul and Catherine will go out next Wed 31 Mar. Paul will return the van to the UK on Sat 3 Apr but will return for Wed 7 Apr to Fri 9 Apr. Catherine will remain until Thu 8 Apr. Following Easter, they will both return. The equipment will remain at Paris until around the end of April. It would be good to have at least two people out at all times when we are testing (i.e. not weekends, when there is no entry to EP). At present for Mon 5 Apr and Tue 6 Apr (and part of Wed 7 Apr), we will have only Catherine there, so if anyone can make it out for those few days, then it would be helpful; let Paul know if so. Following Easter, Paul cannot go out until Fri 16 Apr, so if anyone can cover earlier in that week, it would be good. Finally, in the week 19-23 Apr, there is a LC workshop in Paris which means Paul and Catherine will only be sporadically at EP. Hence, another person during this week would again be useful. Next meeting: To be arranged later, but will not be next week, due to the move out to Paris. It will probably be a phone meeting in the week beginning Mon 5 Apr.