Minutes of CALICE Electronics Phone Meeting, 26/05/04 ===================================================== Present at DESY: Matthew Wing Present at Imperial: Dan Bowerman, Paul Dauncey, Osman Zorba Present at RAL: Adam Baird, Rob Halsall Present at UCL: Matt Warren Minutes: Paul Matters arising: The replacement USB CF writer has arrived at RAL. It should be taken out to Paris by whoever goes out next. There has been no progress on the user guide, but this will have to be produced at some point. Report from Paris: Paul went to Ecole Polytechnique on Fri 21 May for various items. His progress was: o The dev board was swapped to use firmware V8. The UCL one (which had been at EP) was brought back to the UK. The RAL one was installed and left at Paris. A new dev board-backplane cable had been made by Matt and Adam and this was also installed. The IDC connectors at the dev board end did not include wires for an input external trigger to the dev board (as used for cosmics), or an output trigger from the dev board (used for triggering the scope). As an alternative to the former, the BE design has another backplane input for triggers, which bypasses the dev board. However, this has not been tested. The new cable included a ground connection between the dev board and the crate. The crate is grounded through its power supply to the wall power. The dev board is grounded through the RS232 cable to the PC and hence to ground (but not through its power supply). This new cable then gives a grounding loop. However, Adam and Matt had seen problems when using a cable without grounds, albeit with a laptop which may not have provided an adequate ground to the RS232 port. In practise, no problem had been seen previously without this ground connection and the new cable worked for the CERC-only tests which were done both with and without the ground connection. However, it would be worth checking if the noise has any dependence on this connection next time we run with a VFE board. o New firmware was tested on SER002. Osman had put V3.7 and V3.7_1 on the web to download. These seemed to load but the clock LEDs did not start flashing. (There was a problem with the directory structure of the files and Paul had to rearrange these to get the load to occur at all, so it is not clear if a residual file problem was causing the clock problem or not.) Matt later produced V3.7_2 which loaded and had clocks. This had the right file structure to load although Matt had also made a few changes; Osman's FE code is identical. A very brief test of V3.7_2 indicated that the triggers may still be being missed by some of the FEs. However, as Osman had rearranged the output data format to make it smaller, it will require more software work to unpack the new format and hence test this thoroughly. One item which appeared not to work at first go was the link array read, which reported 0xffffffff. SER002 was left with V3.7_2 in the crate so further tests could be done remotely. o VME upgrade on SER001. The VME firmware on SER001 had been changed by Adam to the latest version, 0x1100030f. This allows the LM82 and ADM1025A which are connected directly to the VME FPGA to be read. (The LM82s which are connected to the BE and FEs cannot yet be read due to no firmware.) The LM82 worked fine and reported sensible temperatures. The ADM1025A could also be read and was mainly OK. However, although the local temperature reading was normal, the remote temperature appeared to be unconnected. Rob said this was the case. In addition, while most voltage levels were as expected, the 2.5V channel on the ADM1025A was reading 1.8V and the Vccp channel (nominally 2.25V according to the spec sheet) was reading 1.5V. Again, it was thought these are the actual voltages connected in the CERC implementation and so all appears OK. o Tests of SER001. Using CF V3.5 and V3.6, SER001 was tested. The error which had been seen previously at Paris, specifically the FE clocks stop after RS232 commands are sent, was reproduced with both versions. Following a suggestion from Adam, this was narrowed down to being caused by the BE RS232 reset command. When the reset routine was commented out, the board then worked as expected. Matt said he found this error to be very hard to understand and so this problem needs to be investigated with some urgency. Paul also ran the internal DAC loopback test on SER001 with V3.6 once it was working (see plots on the web). As seen previously, V3.6 has a DAC problem where the value appears to be shifted up by one bit with the MSB being discarded. However, six ADCs on the last FE (FE7, Chips 0-5 in the plots) see a different ADC range as the DAC is scanned; rather than 0 to 15k, they give -30k to 30k. Paul had thought this might be related to the ADC and DAC range changes which had been implemented on FE6 (DACs) and FE7 (ADCs) but Adam pointed out the changes would be downstream of the internal loopback and so only visible in the external DAC loopback test. Dan had previously seen similar behaviour for FE7 on this board; see http://www.hep.ph.ic.ac.uk/calice/elecPrototypeTests/intDacSER001.ps SER001 is now back at RAL and available for testing. [Note added after the meeting: the change to the ADCs was from resistors of 510/510 (=1) to 750/510 (=1.47), a gain increase of 1.47. The change to the DACs was from 510/1000 (=0.51) to 2200/1000 (=2.20), a gain increase of 4.31.] Future tests: The trigger problems in V3.7_2 need to be diagnosed. Paul will try triggering from the dev board, BE and FEs to see if/when the triggers are reliable, although Matt pointed out that FE triggers are synchronous and so even if they work, it does not necessarily locate the problem to be in the BE or dev board. The problems with SER001 also need to be investigated. The first thing is to try to reproduce the error at RAL. This will need a Linux PC (to run Paul's code; it will not work trivially in Windows so Paul will bring his laptop), a dev board (the UCL one, which should be upgraded to V8), a dev board-backplane cable (Adam can produce one), an RS232 cable (Paul will try to find one) and a crate (the CMS one or the minicrate, although there are worries the latter is producing further differences). Matt, Paul and Adam will meet at RAL on Wed 2 Jun to try this out. Any feedback and changes for the FE code need to be specified quickly, as Osman will be on holiday from Mon 7 Jun to Fri 25 Jun inclusive. Rob has not yet got a decision on Saeed's effort for the BE but this should be done soon, probably by going through Steve Quinton. SCSI cables: Bernard Bouquet (who is making the ECAL mechanical support) has looked into the cable length required and has specified it needs to be >2.3m. Hence, it seems we need to buy 3m cables and so this can be done now; this is helpful as the ones we have borrowed from Renato Turchetta need to be returned soon. Adam had quoted 30 pounds/cable in the previous meeting for 1m cables; the 3m cables will probably be more like 40 pounds/cable. He will get a price for 70 cables (60 plus 10 spares). PCB changes review; A decision on which changes are needed for the PCB must be made soon to allow the DO to complete the relayout by the end of the slot which has been booked, i.e. the end of July. Also, the FE FPGAs need to be ordered (they would already not be here in time for an August assembly if there is really a 15 week delivery time) so a decision on which component, the 500 or 1000, is needed asap too. Rob had previously suggested dedicating a meeting to a review of the changes. This needs to be scheduled within the next week or so. The day of Wed 2 Jun was chosen, starting at 10.30am. (The SER001 tests can take place before and/or after the review.) Adam will go through all the known PCB issues and decisions on what to do with them should be made. Clearly, there could be other problems found in the BE region as testing continues, although we are getting more confident most of the FE problems are known. Test board: Matt asked whether there was still a need for a test board. Paul thought yes, as the board currently used for external DAC loopback is not very easy to use; to change channels requires someone to physically move the connector. There is also a likely need for a back-of-crate card for the trigger I/O to J0 and J2. Paul, Matt and Martin should meet to discuss this. Next meeting: This will be the PCB review on Wed 2 Jun at 10.30 at RAL. Rob and/or Adam will find a room.