CALICE Electronics PCB Changes Review, RAL, 02/06/04 ==================================================== Present: Adam Baird, Dan Bowerman, Paul Dauncey, Rob Halsall, Matt Warren, Osman Zorba Minutes: Paul Problem reports; The 38 problem reports as listed on Adam's web page http://www.ins.clrc.ac.uk/esdg/calice/problems/index.html were discussed in order. PR001: This was identified and fixed before the prototypes were fabricated. PR002: It is not known if this is a real issue or not. If it is, then the only feasible solution would be to change the voltage regulator used (preferably to a pin-to-pin compatible component). Adam will check the regulator specification and look for possible alternatives. PR003: This is a BE change of just one physical track and so should be straightforward to implement. PR004: The current understanding of the DAC range is that the VFE PCB will only need unipolar DAC voltages (but will probably not be damaged by negative polarities, just go into saturation). It is also likely to implement the signal range change so as to use the whole of the ADC range, not just the top half. The internal and external DAC loopback ranges can be set separately. The internal DAC loopback is a channel check for DAC setting and ADC readout but, as it uses a different path from the real signals, will not be usable for actual gain measurements. The external DAC loopback is (currently) done by jumpering the DAC voltage to each input channel in turn; with a unipolar DAC output, this would require the jumper to be inverted to get negative voltages. (In the future, an active test board might be able to do the channel selection and inversion under computer control.) The choices are to leave the DAC as it is, to change to a new component which allows true bipolar voltages (such as the AD5542) or to adjust the op-amp to shift the differential output negative. Any different DAC would have more pins and so would require a significant change to the layout; the op-amp change would be likely to be as major. Leaving the DAC as it is would prevent an internal loopback check of the whole ADC range (probably not a necessary check) and make the external loopback less convenient. It would be well matched to the VFE needs. Given the work needed to implement the changes, it was thought this should not be changed, so the DAC will be left as is. The saturation at low DAC values does need to be fixed; this will require a new line to the low end of the op-amp and so is a FE layout change. The actual values of the DAC (and ADC) ranges to use depend on the VFE PCB V3 tests which should take place this month. PR011 is related to this issue also. PR005: This is related to PR007 and PR025. The whole power/reset part of the board has not worked reliably. The changes needed cannot be finalised until the problem is understood; this is one of the major issues outstanding and needs to be investigated and settled asap. PR006: Straightforward and will be done. PR007: See PR005. Matt partially fixed the reset problems by handling the reset differently in the BE firmware. However, the reset problem still exists. PR008: Labelling, so straightforward to change. PR009: This requires changing the values of resistors only, so is straightforward. PR010: The FE I2C bus needs two pull-up resistors per FE; the BE and VME buses are correct. This should be straightforward and will change the FE module layout. PR011: See PR004. This changes the resistor values only and so can (in principle) be decided after the relayout has started. Each DAC needs two pairs of resistors specified, one for the internal and one for the external loopback. PR012: This must be done and is straightforward. PR013: The VFE pull-ups cannot be done in the FE Xilinx and so need to be added. This requires eight new resistors per FE module and there should be sufficient room to place them. This is a FE module layout change. PR014: The two pins identified (W16, Y16) were originally noticed when Osman compiled his firmware for the 500 component. However, these are not the only two pins being used which are not available on the 500; there are others which he was not using at the time. Hence, to change to being able to use the 500 would not be trivial. The cost differential between the two is likely to be around 20 pounds, meaning around 120 pounds per board (out of 8 kpounds) or 1.5 kpounds total for the system. This is relatively small and so is not a major factor. The more important issue is the lead time to obtain the FPGAs, given the 15 week lead times which have been mentioned previously. Unless there is a major time advantage to getting the 500, then we should go with the 1000. The assumption is then that this change will not be made and that Rob will check the prices and times on these components and order the 1000s asap. PR015: This is straightforward and will be done. PR016: This is also straightforward and will be done. PR017: The actual fuse values needed have to be measured, otherwise this is straightforward. PR018: This is mainly modifying the assembly instructions and so will be done. PR019: See PR004 and PR011. PR020: This is not an issue except that it is not clear if the QDRs for all nine production boards are in hand. This should be checked. PR021: Straightforward and will be done. PR022: It is thought that enlarging the holes can be done without disrupting the tracks around the holes; if so, it is straightforward. Otherwise, it might be a significant relayout job. PR023: This is a reasonable amount of work as it is not a step-and-repeat task for each FE module. This could take some time to do well. It should be done as long as there is time. It is a relayout of the BE. PR024: The change to the R and C pads involves several 1000 pads and so is a major task. The pads for these components would also have to be put as different shapes for those under the FPGAs as space under the BGA is very limited. This could be a major task; while checking for good solder joints could catch some critical problems, this has not been standardly done for any boards previously. One approach might be to enlarge the pads for a smaller number of critical components. It is a change to both the BE and FE module layout. PR025: The hot swap LED is the (only) LED on the front panel. This was the modification done by Saeed some weeks ago. Adam is not convinced the fix was appropriate and it has been backed out. The problem is similar to one seen by CMS; they have an equivalent problem report. It is probably related to the reset problem in PR005 and PR007; again a solution must be found before any change can be defined. PR026: Straightforward and will be done. PR027: This is essential to ensure correct QDR operation and so must be done. If this pin does not float high, then the QDRs might not function on the prototypes at all. This is a change to the BE layout. PR028: This is straightforward to change but it is not really necessary. Only if there was a plan to extend the component family and we wanted to plan for this extension would it be worth doing. As this is unlikely and we are short on time, this should not be done. PR029: This is an assembly issue and will be done. PR030: Smaller LEDs (not bigger pads, which would require relayout) will be used. PR031: If confirmed obsolete, then Adam will find a pin-to-pin compatible alternative. If not, the this will require retracking; there are eight per board. This would then be a FE module layout change. PR032: Again, the status should be confirmed but given the number in hand, it seems unnecessary to change the layout. PR033: This is essentially a clean-up task. Removing the components from the layout seems risky (albeit low risk) for no benefit at all. It would be preferable not to change the layout at all but simply not to mount the components; the only issue is how to implement this automatically. PR034: This needs to be checked to see what it would mean for us before any changes could be decided. PR035: These are all straightforward and will be done. They are all BE layout modifications. PR036: Again, these need to be checked to see what they would mean for us before any changes could be decided. PR037: Straightforward and will be done but will be a layout change. PR038: Straightforward and will be done. Other items: Matt raised two further items: o The silkscreen labels on the BE LEDs are not appropriate for CALICE use. These should be changed to numbers rather than labels. o The QDR signal names on the schematics are not very appropriate; QDR2_Q8 is missing, so the data bits are Q1-7 and Q9-17. Paul raises a minor item, which was that the front panel FE numbering should be FE0-7, as physically implemented on the FE lines and hence read out, as opposed to FE1-8. Adam will add these to the problem reports list. Next steps: The things to be done next are; o Rob will check with the DO (specifically Chris Day) about the feasibility to do these changes by the end of July, bearing in mind there could be more depending on the results of the BE tests. If the above is considered too much given the time, we need to prioritise the changes. o Rob will work out whether we can get help from Saeed to get the BE firmware working and so test the remaining parts of the board. o Rob will check on the lead time for the Xilinx FE components and be sure the 1000 parts are available on the right timescale. o Adam needs to diagnose the power/reset problems (with James Salisbury) so as to discover if any changes are needed. o Adam needs to check for the implications of the uncertain items referred to in PR002, PR034 and PR036. o The remaining components should be ordered; these are the QDRs (if we do not have sufficient for ten boards), the FE Xilinxs and the (possible) obsolete/replacement parts referred to in PR002, PR031 and PR032. o The 3m cables should also be ordered.