Minutes of CALICE Electronics Phone Meeting, 15/07/04 ===================================================== Present at DESY: Matthew Wing Present at Imperial: Paul Dauncey, Osman Zorba Present at RAL: Rob Halsall, Saeed Taghavi Present at UCL: Matt Warren Minutes: Paul News: Paul reported that he had brought all the equipment back, including SER001, from Ecole Polytechnique to Imperial on 06/07/04. It has been set up in the lab in Imperial and seems not be to damaged. To keep track of things, the dev board in this system belongs to RAL but its power supply belongs to UCL. Drawing Office status: Rob reported that all known tracking and component changes which we decided to make have been implemented. This includes the retracking of the FE-BE signal lines. The silkscreen changes are still to be done. We have not yet tested all parts of the board, particularly the BE. In addition, the power-up/reset issues are still being investigated. Hence, we must assume further changes will be discovered to be needed as these items are checked. The CALICE overall schedule requires us to be able to read out the first stack of ten layers in Oct, with the second stack of ten layers being ready in Nov and the third in Dec. Each stack is ten full, five RH and five LH VFE PCBs which requires 15 FE inputs and so just fits into two CERCs. This means ideally we would have made and full tested at least two production CERCs by the end of Sep, which requires testing in Sep and so fabrication and assembly in Aug and so to be finished in the Drawing Office by the end of Jul. However, if we do not find significant problems with the two prototypes, then we could use these temporarily instead for the first stack and so give ourselves some extra time on this schedule. Hence, assuming the prototypes are usable, the Drawing Office should try to complete by the end of Aug, so the fabrication and assembly is finished by the end of Sep and the testing complete by the end of Oct. The work is now being done not by Chris Day but by Darren Ballard. Rob will find out his holiday times so we can plan around them. Even on this schedule, it might be prudent to stagger the fabrication and/or assembly of the PCBs. We should consider only completing two CERCs initially, which is enough for one stack and so allows the others to be done a month later. Whether this preproduction is done by fabricating only two PCBs initially, or by fabricating all nine but only assembling two, depends on the relative costs. The PCBs costing we had previously was very expensive and so two PCB fabrication runs might be prohibitive. We will consider this when firm quotes are available. Outstanding issues: It is clearly important to identify any remaining PCB modifications needed asap so that the Drawing Office can incorporate them. (This work takes priority over long-term firmware designs for the final system, which can be done after the boards go out for fabrication.) The issues which need to be tackled are the power-up/reset problems, the testing of the whole BE/VME region and the testing of the remaining FE components (mainly the FE LM82s) and FE-BE signal lines. Saeed reported that he had modified the CMS FED BE firmware to run in the CERC. He removed all the TTC code and has only enabled triggering in scope mode. Using this, he has been able to write counter data into, and read it back from, the QDRs on SER002. He can read the BE registers using the serial commands driven from VME. He has not yet checked the BE LM82. The latest VME firmware version is still 0x1100030f, which is also the one installed in SER001 at Imperial. He has not put anything into the FEs and so none of the FE components can be checked yet. Osman will meet with Saeed to get the FE command module and I2C bus firmware so he can incorporate it into his FE design. This will then allow the remaining FE parts to be tested. Matt will consider how to do high frequency tests of the BE to backplane connectors, which are needed for the trigger I/O. Saeed also reported that he had found a problem which is probably causing the power-up to not boot the FPGAs reliably. This will require a PCB layout change and so should be reported to the Drawing Office asap. Unfortunately, it cannot be implemented on the existing prototypes. Matt asked that the netlist and schematics corresponding to the most recent version implemented by the Drawing Office should be distributed. Osman and Matt will go to RAL on 19/07/04 to meet with Saeed and discuss how to incorporate the FE command and I2C modules into Osman's FE design and the trigger module into Saeed's BE design. Paul cannot attend as he is going to SLAC next week, but this is not important for this work anyway. Next meeting: A phone meeting at 2pm on Thu 29 July. Call the same number as for this meeting: Within the UK 0871 438 8326 Outside the UK +44 870 438 8326 and use the same conference room number 570769 and passcode.