Minutes of CALICE Electronics Phone Meeting, 29/07/04 ===================================================== Present at DESY: Matthew Wing Present at Imperial: Dan Bowerman, Paul Dauncey, Osman Zorba Present at RAL: Adam Baird, Rob Halsall, Saeed Taghavi Present at UCL: Martin Postranecky, Matt Warren Minutes: Paul Matters arising: We need to be aware of Darren Ballard's holiday plans so as to schedule the Drawing Office time around them. Adam reported he would be away from Fri 20 Aug to Wed 1 Sep inclusive. Hence, the Drawing Office work has to be finished before this time. Matt had requested the updated schematics and netlist for the modified board; these have not yet been made available but will be put on the web. Drawing Office status: All of the known changes we have identified are now entered and these could be completed by the end of the week. In addition, there are a few other changes which CMS have identified for the FED which Adam has checked and need to be implemented for the CERC also. Some more changes might be found to be needed as the remaining parts of the board are tested over the next few weeks. The question is how to deal with this for the Drawing Office. Given that Darren Ballard will be away from Aug 20, then the plan is for him to complete the board before he leaves with as many changes as are known about by that time. (In fact, he will need to complete in time for the review, see below.) This should allow anything found in the next week to be included. If further changes are then discovered after he has left, then we will have to decide if they can be fixed with a cludge to the board or are important enough to hold up production. However, the hope is that any remaining issues found will be minor. Remaining tests: Following the last meeting, Paul had taken Saeed's BE-only design and successfully read out all the BE serial information, the QDRs and the BE LM82 on SER001 at Imperial, confirming Saeed's work that these were functional on SER002 at RAL. This means the things which are still to be checked or solved are: o The FE-BE communication at speed. o The FE I2C bus operation, i.e. the FE LM82. o The remaining QDR address lines. o The trigger-backplane connections at speed. o The longstanding power-up/reset FPGA unreliable reload problem. Osman hit problems with the link array readout and so has not had time to use Saeed's FE command module and I2C bus control. Hence, the FE-BE communication and I2C tests are still to be done. Osman will try these within the next few days. The link array problem was that the pull-up resistors did not seem to be doing their job and the levels were being left in an intermediate state. This is not yet understood but might require the pull-up resistor values to be changed. There are two unconnected QDR address lines in Saeed's firmware version, as the CERC needs more address space than the FED. The test which is required now is to use those two lines instead of two which are currently connected. This will then allow a speed test of them. Saeed will send the relevant files to Osman and Matt and one of them will do the simple changes to use different address lines. The longer-term solution (which is not needed before the CERC production but will be needed before a real beam test) is to use all address lines at once, which requires a significant amount of firmware work. Saeed will not be able to do this within the time he has available. Hence, this is one task which must be done by whoever from RAL takes this on after Saeed. Rob has not yet found a replacement; Ed Freeman had been mentioned but now looks like he will not be available. Matt is setting up for the BE-backplane check. He was hoping to find a commercial board which would fit on the backplane connectors but has not succeeded and so will solder some wires into connectors. He was wondering if single-ended, unterminated signals over the short BE-backplane distance would be sufficient for the test; the consensus was that this was probably OK. Both the J0 and J2 connectors will be tested. Matt will come to Imperial to sort out some software to peek and poke BE registers via VME serial commands so he can set and test the backplane connections using BE registers. There seems to be little progress on understanding the power-up/reset errors. The problem reported by Saeed in the last meeting would not in fact affect this at all. He found the DONE line is taking too long to come up and the FPGAs were looking at it too early. This can be fixed by either changing the resistors on this line to allow it to come up quicker, or by a firmware change to pipeline the signal and so sample it later. Adam would like to see if this has any effect on the reset so the firmware fix should be implemented; this was thought to be straightforward. For the production version, Adam has already implemented the resistor change. Other items: Adam reported that the VME-BE FPGA clock should be differential. CMS use a single ended signal but the CERC has termination resistors installed. The intention is for CMS to move to differential so Saeed will modify the VME firmware to include this change now, so we can test it on the CERC. This should be the only difference needed between the VME versions for the FED and the CERC. (Saeed has renamed some of the signals on the schematic but not changed their functions.) Paul asked if there was some documentation on the VME address space used for accessing the SystemACE registers. Saeed will send Paul what he has on this. Adam was concerned that the BE-VME clock must always be ignored by the VME FPGA on the CERC board (although this path is used on the FED). This is indeed an issue which needs to be tackled in the final firmware design; Adam is not suggesting removing the tracks for the production PCB. The hot swap switch has never been enabled; Adam will check if this has any impact on the reset problem. It should be possible to get a much firmer fabrication price now that the board is nearly complete. Also Adam has stripped off all the TTC components, which has reduced the component count and might make assembly cheaper. Holidays: Paul is away from Aug 2 for two weeks. Matt is away from Aug 14 for two weeks. Final design review: The review must be held in time to allow Darren Ballard some time to correct any mistakes found before his holiday. Hence, it needs to be around a week before he leaves. Fri 13 Aug at RAL was chosen; Paul will be not be able to attend so Rob will organise this. Next meeting: The next normal meeting will be the week following the review on Thu 19 Aug at 2pm.