Minutes of CALICE Electronics Phone Meeting, 19/08/04 ===================================================== Present at DESY: Matthew Wing Present at Imperial: Paul Dauncey, Osman Zorba Present at RAL: Adam Baird, Rob Halsall Minutes: Paul Design review: This had been scheduled for Fri 13 Aug to give Darren Ballard time to incorporate any changes before going on holiday tomorrow (Fri 20 Aug). However, the review was subsequently rescheduled to Tue 17 Aug. Adam, Rob, Osman and Saeed attended the review. They went through the circuit and problem reports and several minor changes were identified. The documents for the review can be found on Adam's web site at: http://www.ins.clrc.ac.uk/esdg/calice/review/mk2/idr1/index.html although there is no explicit list of the changes there yet and this needs to be added. All the changes have already been incorporated into the layout by the Drawing Office. However, because of the delay in the review, the Drawing Office are only now doing the gerber step and the assembly and drilling diagrams still need to be done. Hence, it is unlikely this will be finished today. There will therefore be a two week delay until Darren Ballard gets back from his holiday on Thu 2 Sep. A quote for the PCB fabrication and assembly (done at the same company) from DDI can take up to a week, so Darren must request that before leaving today. The quote should be returned to Rob in Darren's absence. It should ask for the price for various turnaround times. In addition, while we will make all nine PCBs in one go, prices for assembly of all nine compared with assembling two initially (for testing) followed by the other seven later will be needed, as discussed previously. Adam will check with Darren after the meeting that all these options are requested in the quote. After the layout is complete, there should be an internal Drawing Office review, which will be done by Dan Beckett. This will be done on whatever is completed by Darren by the time he leaves, so as to not delay things further when he returns. Remaining prototype checks: There is a list of five outstanding items which should still be tested on the prototypes: o The FE-BE communication at speed. o The FE I2C bus operation, i.e. the FE LM82. o The remaining QDR address lines. o The trigger-backplane connections at speed. o The longstanding power-up/reset FPGA unreliable reload problem. Osman has tried using Saeed's FE command decoder for reading the FE LM82s. The FE part seems to function correctly with the I2C busy bit being set but all data sent back from the LM82 are zero. Adam suggested checking if the FPGA internal pull-up resistors are enabled on the I/O pins as I2C requires pull-ups and there are no external ones for these signals. Osman has only got the code to run at all on FE0 and thinks the clock outputs from the BE might not be enabled for the other FEs. The previous RS232 firmware system used the differential FE-BE clock lines so we are sure the hardware is functional. In principle, Matt's latest BE version might be better but Osman cannot get this to load. Matt was busy with Atlas work before the start of his holiday and was not able to cover everything he wanted to try. There has been progress on the preparations for the FE-BE, QDR and trigger-backplane tests but they still need checking. Matt sent the following status report: o I have spent good time with the schematics/netlist and think the trigger backplane IO looks fine. o We've added lvds fanout buffers to the board, so that 2 lvds signals are duplicated 10 times each and placed on the J0 connector. This facilitates easy intra-crate trigger/clock fanout. o I've hashed together a backplane loop-back board, but it remains untested. It has IDC connectors to bring signals out too. o I did manage some new BE code in the end, it has all the Saeed stuff, with correct pinouts (I hope). o The BE Trigger block now has 15 r/w 32 bit registers for future trigger functionality (target 9, desigs 1-15). I tried them out at IC and they work. o I met with Saeed and he now completely understands how we want the trigger data included (he had thought it was coming from FE's). He thinks it a big job, although there is room to fit much smalled blocks into the existing framework. Adam and Osman have been looking at the power-up/reset problems. Osman reported that, using the CALICE crate at Imperial, the CF code seemed to load reliably on FED002 on power-up but not on the CERC. In addition, the reset button works on the FED and not the CERC. Hence, the problem is not likely to be a difference between the CMS and CALICE crates. Osman also saw that the CERC does not always load when the CF card is removed and reinserted; he saw it worked better when the reset button is pressed first. (This is a new problem which has not been observed previously.) Adam had suggested soldering on a 2.2uF capacitor to lengthen the power-up delay but neither he nor Osman had been able to find one which will fit. Paul and Matt (mainly by trial and error) managed to get the board to reboot using the VME System ACE interface. There seemed to be a persistent switch which disabled and enabled the firmware load even after a power down, although Adam suspects just that the power down was not long enough to fully discharge the board. Paul had difficulty understanding the documentation on the System ACE which he had and Rob will ask John Coughlan to help; CMS have had this working in the past. Holidays: Matt is currently away and returns to work on 31 Aug. Adam goes off tomorrow (20 Aug) and returns to work on 2 Sep. Next meeting: This should be just when the production is ready to go out. Hence, it will be a phone meeting at 4pm on Mon 6 Sep. Use the same conference number as today.