Minutes of CALICE Electronics Phone Meeting, 21/09/04
=====================================================
Present at Imperial: Dan Bowerman, Paul Dauncey, Osman Zorba
Present at RAL: Adam Baird, Rob Halsall
Present at UCL: Mark Lancaster, Matt Warren

Minutes: Paul


Matter arising: None.


Production status: DDI have said they will need seven days to do the PCB
 assembly rather than five, as they need to outsource the connector
 press-fitting to another company. They will obviously charge us the
 (lower) seven day turnaround cost. It means both fabrication and assembly
 steps should take seven working days each. The order went in on Wed 8 Sep
 and so the fabrication should have been completed yesterday and hence
 assembly started today.

 DDI have received the assembly kit and instructions and should have checked
 these before they start the actual assembly. Assuming there are no problems,
 we could expect the boards at RAL before the end of next week.

 The JTAG tests should only take a few days if everything is OK on the two
 boards being assembled. However, the front panels will be delayed and Adam
 will chase these up. In addition, the strengthening bars need to be made;
 these were made by Ivan Church for the prototypes and he should go ahead
 and made all nine in one go asap.

 If everything goes well, the boards should be ready to come to Imperial
 by the week of Mon 4 Oct. Paul will organise collecting them in person
 rather than using a courier.


Firmware status: Osman has discussed the FE->BE event data protocol with
 Rob and the synchronisation of the data from all eight FEs is a potential
 issue. Each FE needs to send a FrameSynch command to the BE when it is
 ready to send its data. However, it may be that all eight of these commands
 need to arrive at the BE on the same 40MHz clock tick, which would require
 some time alignment. (It is not clear if this is really required and Saeed
 should be involved in this discussion.) Possibilities for synchronising 
 the FEs were discussed, such as sending a synchronised second trigger to
 the FE immediately after the real trigger, or using the falling edge of
 the trigger signal. Synchronising the trigger to a 320MHz clock in the BE
 might not get round the problem.

 Rob will check with Saeed and organise a meeting at RAL of Saeed, Rob,
 Osman and Matt to come up with a solution. This needs to be done asap
 and certainly by Mon 27 Sep at the latest.

 Saeed has done nothing on the QDR address lines; Rob was not sure when
 he would be available to do this work.

 Matt reported that the problem seen with the other FEs than FE0 on
 the prototype board at Imperial was due to old firmware in the FEs.
 With a newer version, they all work correctly.

 Matt will not be supplying firmware to define registers in the FE; some
 items like event counters will be needed and these should be added by Osman.

 Paul pointed out the minutes of the previous meeting had details on the
 work needed and which parts would be needed first; this should be checked
 by the people involved.


HCAL production: The HCAL DESY group have asked about the cost for producing
 six or seven CERCs. Paul was not sure of their timescale but guessed they
 might be required by Feb or Mar next year; Rob should check with Felix
 Sefkow, the DESY contact. The main thing needed currently is a reasonably
 accurate price.

 They plan to use try to use just the ECAL firmware although they may need
 some adjustments; DESY effort might be available for this.


Next meeting: Tue 5 Oct at RAL, starting at 1pm  Assuming all goes well, the
 boards should be ready for collection to take to Imperial by this time.