Minutes of CALICE Electronics Phone Meeting, 13/10/04 ===================================================== Present at Imperial: Paul Dauncey, Osman Zorba Present at Manchester: Dave Mercer Present at RAL: Adam Baird Present at UCL: Matthew Wing, Matt Warren Minutes: Paul Board status: The expected date for the boards to be returned to RAL is now Fri 15 Oct. DDI initially had machine problems which required them to move the job to a different machine. They then found the top solder paste layout was wrong and had to remake this. Neither of these problems should cause a delay when we assemble the remaining seven boards. The wrong capacitors were sent, having a rating of 16V rather than 25V, but as the maximum voltage on the board is 12V, this is still acceptable. We could send the correct capacitors for the other seven boards. Adam commented that he has not been impressed by the feedback from DDI. It has been sporadic and unsystematic; he often got no response from DDI to queries and most information has come through Viraj Perera, who is now handling the one-stop PCB manufacturing for RAL ID. Assuming delivery on Friday, then this will be 18 working days, compared to the 5 requested. RAL will request the 15 day cheaper price for this turnaround (3398 compared to 4248, a saving of 850 pounds) but it is not definite this request will be honoured. The JTAG will then start early next week; Adam and Richard Matson will be doing these tests. The boards should be collected to go to Imperial as soon as the tests are complete, so Adam will keep everyone informed as to progress next week. Outstanding issues: There were two items raised via email since the last electronics meeting: o The FE<-->BE I/O lines. Osman had questioned whether the 14 physical lines between the FE and BE were sufficient. However, one of the CMS signals has been dropped; Frame_Sync_In is not longer needed. Hence, one of the handshake lines is redundant and 14 is indeed sufficient. Our use will remain compatible with the CMS BE code. The list of the 14 connections (IMOD10-19 and IMOD110-113) is: From the FE to BE DATA 4 lines CONFIG_OUT 1 line FRAME_SYNC_OUT 1 line READOUT_SYNC_OUT 1 line ------- TOTAL 7 lines From the BE to FE CLOCK 2 lines (LVDS) TRIGGER 2 lines (LVDS) RESET 1 line COMMAND_IN 1 line READOUT_SYNC_IN 1 line ----- TOTAL 7 Lines o The FE-->QDR data synchronisation. Matt and Osman have settled on using the falling edge of the trigger as the synchronisation marker. This can be made close enough to the 40 MHz clock that it will be seen on all FEs on the same clock tick. Matt has built in some simple phase adjustment in case it is needed. The Frame_Sync_Out needs to be issued at the same time from all eight FEs, synchronised from the falling edge. This will probably need some delay to ensure the data are not send until after the digitisation sequence is complete and the FE FIFOs are filled. Osman will check this with Saeed Taghavi. Note, the trigger rising edge, which gives the trigger timing itself, is still asynchronous. FE firmware status: Osman has incorporated major changes to the FE firware recently. He had found a bug in the command module which is now fixed. He has implemented an A10/D16 system for the VFE control registers and fake event data. There are a few outstanding issues, e.g. the MSB of the fake event words is lost, but it seems to be mainly working. He will move the VFE and fake event configuration to A10/D32 and make the counters 32 bits also in the next version. The FE should never see a second trigger while it is going through the ADC sequence. In case this is not adhered to, it is not clear if the FE should gate the trigger input or not, and if so, whether the counter should count before or after the gate. This should not be an issue if all is working well. Osman also thinks the double data rate firmware to send the FIFO data to the QDR is working, but this part still needs to be tested. BE-trigger firmware status: Matt has defined a serial interface for the BE trigger section and will distribute the list of serial commands. His code to implement this loads but has not been tested yet. Osman commented that it had stopped the clock to the FE when he had tried the previous version. BE firmware status: Dave will work with Saeed on implementing the extra two address lines (A19 and A20) we need to extend the QDR memory from 2MBytes to 8MBytes. Saeed is concerned that the two sets of BE code (for the FED and the CERC) are diverging. This may be inevitable; however CALICE does not need all the bells and whistles which CMS will want and so if we get a version which does what we require, then we can maybe get away without the further CMS improvements. VME firmware status: Saeed circulated a new version of the VME firmware, but this has not yet been installed on the CERCs. This should be done soon. AOB: Matt will be at the IEEE conference in Rome next week presenting a poster on the CALICE-UK electronics. He will circulate this when it is ready. [Note added after the meeting: it can be found at http://www.hep.ucl.ac.uk/~warren/calice/poster_big5.jpg ] We will need inter-board back-of-crate connections to distribute the trigger to (initially at least) two boards before we can go to Paris. The argument for a dedicated back-of-crate PCB is reduced since the production version of the CERC has two 10-way fanouts between the BE FPGA and the J0 connector for trigger use. Matt and Osman will decide how this should be done and Imperial will make any simple PCBs needed. We have borrowed some small drift chambers for tracking in the DESY test beam. These will need eight TDC channels to read out and a VME module is needed. This needs to be at least 10 bits. Paul has tried to borrow one, but with no luck so far. Something like a LeCroy 1176 would be ideal. Matt mentioned there might be a TDC module left over from the MINOS prototype beam tests which we might be able to borrow. Another possibility would be to buy one, although Matt thought they might be very expensive (~5k), which would put them beyond what we could afford. Dave asked for the latest schematics for the CERC production version. Adam will circulate these. [Note added after the meeting: they can be found at http://www.ins.clrc.ac.uk/esdg/calice/review/mk2/PC3252m2/schematics080904.pdf ] Next meeting: A phone meeting on either Wed 27 Oct or Fri 29 Oct, depending on when Adam is available. [Note added after the meeting: it will be at 1pm on Wed 27 Oct.]