Minutes of CALICE Electronics Phone Meeting, 09/02/05 ===================================================== Present at Imperial: Paul Dauncey, Osman Zorba Present at Manchester: Dave Mercer Present at RAL: Adam Baird Present at UCL: Matt Warren Hardware status: Adam reported that all seven production boards passed JTAG tests with only minor problems identified. One error was a missing resistor on the link array of one board; there is a bad pad next to it which may have caused the problem. Several of the boards had 3 or 4 bad pins on U19 which is the EPROM next to the VME FPGA. All the power supplies seem OK. Several mechnical parts are missing. All the jacking screws for connecting the cables to the front panel connectors are still at DDI (although they have now been requested back). The strengthening bars have not been made; they were requested but never delivered. It is not clear who is responsible at RAL for making these now. There is a board error which means there is no hole for the mechanical screw to be inserted to hold the CF eject mechanism. These are therefore held on by their solder only and so should be treated carefully. Adam will try to add solder to reinforce the join. Matt has set up a 9U crate at UCL with a PC running RH 7.1 Linux and a NI VME card. This should be capable of being used for testing the boards. Paul and Matt will install and test the code next week The same version of the VME firmware as used on the other boards, V21_03_16, should be loaded onto all seven of the boards. Collection to get them to UCL will be arranged soon. The AHCAL people will buy the same boards for their readout. This means we will need to leave at least eight cables at RAL for their future JTAG tests. We will need extra CompactFlash cards; Imperial will order more. No particular make is needed. FE firmware status: Osman reported there are three known issues: o The VFE PCBs draw a lot of current if left in the wrong state. The HOLD needs to go high after a reset to prevent this. o The framesync needs to be more reliable. o The failure of FE0 on SER003 (due to a reset of the DCMs?) is still not understood. A failure of FE1 on SER004 looks similar; this one failed after running for several hours in a few of the runs from the DESY test beam. BE firmware status: There is a fix for the dropped triggers from Saeed which has been reimplemented by Matt in his version and needs to be tested. Saeed has made quite a few other small bug fixes since the version Matt originally started from. The big issue looming is whether to try to reimplement Saeed's changes into Matt's version or to reincorporate all of Matt's changes on top of Saeed's latest version. It would be quite a bit of work to do either of these but we would benefit from Saeed's recent work. To use Saeed's latest version directly would require moving to a new Synthesis version, i.e. from V5.4 to V6.3. To store 2k events in the QDR requires two sets of changes, firstly to the QDR address lines to use the extra two lines and secondly to the control FIFOs in the BE as they do not have room to be expanded from 512 to 2k long. For the latter, the amount of data in the FIFOs needs to be reduced. One place to cut this down is the 80 bits sent from each FE to the BE every event, which is currently set to 0x010203...0a and has no real use. Matt could send fixed values to the VME FPGA to prevent downstream problems if/when these data are suppressed in the BE. Dave is still trying to simulate the address lines and so has no code to be tested. He should try to compile and download the existing code asap to check that the whole loop works. BE-Trg firmware status: If all seven boards look good, then we will have sufficient spares that Matt could use a board for the BE-Trg only. This would allow him to pipe the trigger data into the QDR via a FE path which might be simpler to implement. This would still be a reasonable amount of work. DESY running: Things are going well at DESY except shift coverage is difficult. Dave is going out for 20/21 Feb, Matt for 22-24 and Paul for 23-25. Next meeting: To be arranged by email.