* FEDv1 Address Table JAC 12.08.03 ************************************************************************************* * key AM width address mask read write description ************************************************************************************* ARGUMENT 09 4 00000000 ffffffff 1 1 Argument data block * SERIAL_BRAM : Serial Command Block RAM start (2 KBytes) WRITE 09 4 00000800 ffffffff 0 1 Write trigger block * SERIAL_WR_CTRL : Serial Command Write ctrl READ 09 4 00000804 ffffffff 0 1 Read trigger block * SERIAL_RD_CTRL : Serial Command read ctrl * ROUT_BUF_LEN 09 4 00000820 ffffffff 1 0 Event Fragment Length in Readout Buffer (in 32 bit words) * (only valid when ROUT_BUF_RDY is set) ROUT_EVT_CTR 09 4 00000824 ffffffff 1 0 Event Number (1st event = 1) ROUT_EVT_LEN 09 4 00000828 ffffffff 1 0 Total Event Length in Readout Buffer (in 32 bit words) * (only valid when ROUT_BUF_LAST is set) ROUT_BUF_RDY 09 4 0000082c 00000001 1 1 Readut Control/Status : = 1 means buffer to read ; clear for next buffer ROUT_BUF_LAST 09 4 0000082c 00000002 1 1 Readut Control/Status : = 1 means last buffer in event ; clear for next event * FIRMWARE_ID 09 4 00000830 ffffffff 1 0 Firmware version in VME FPGA CLOCK_SEL 09 4 00000834 00000007 1 1 Clock Select : Bit 0 = On board crystal ; Bit 1 = TTC ; Bit 2 = Backplane * (NB writing to this has side effect of doing same action as FED_RESET!) FED_RESET 09 4 00000838 ffffffff 1 1 Writing anything to register resets FED VME_STATUS 09 4 0000083c ffffffff 1 0 VME status, bits to be defined * TTC_CLK_CTR 09 4 00000840 00000fff 1 0 12 bit counter on TTC clock BP_CLK_CTR 09 4 00000844 00000fff 1 0 12 bit counter on Backplane clock * * ROUT_BRAM 09 4 00008000 ffffffff 1 1 READOUT_BRAM : Event Readout Buffer Block RAM start (single reads) (32 KBytes) * ROUT_BRAM_BLT 0B 4 00008000 ffffffff 1 1 READOUT_BRAM : same for Block Transfer * *************************************************************************************