Minutes of CALICE-UK meeting, Birmingham, 13/11/01 ================================================== Present: Roger Barlow, Jon Butterworth, Paul Dauncey, Chris Hawkes, Steve Hillier, Ray Thompson, David Ward, Nigel Watson Minutes: Paul Paris Meeting and Travel Budget: The Paris meeting at Ecole Polytechnique is arranged for 9.30 on Tuesday 4 December. It is potentially expensive; the people who will go are Birmingham - Chris Hawkes, Steve Hillier, Nigel Watson Cambridge - Mark Thomson, David Ward Imperial - Paul Dauncey Manchester - Ian Duerdoth UCL - Jon Butterworth (plus A.N.Other?) which is eight (or nine), although Nigel has his own source of travel funds. Eurostar day return tickets are 298 pounds and the first sensible train gets to Gard du Nord at 9.30. Flights might be cheaper, but Charles de Gaulle airport is at least an hour from Ecole Polytechnique. Overall it will be at least 2kpounds. Action: Paul will ask Jean-Claude Brient if the meeting start time can be moved to 10.00 or 10.30. Assuming we have two or three more UK meetings in this FY (i.e. before March) then we could easily use up another 1-2kpounds on UK travel. The next ECFA/DESY series meeting will be in St Malo on 12-15 April 2002, which is after the end of the FY. There is an LC meeting in Chicago on 7-9 January 2002 but there seemed little prospect of any of the people present attending. Paul has asked Ken Peach for 4kpounds for travel for the rest of the FY, but no reply has been received. [Note added after the meeting; Ken Peach has said he will consider a figure more like 2.5kpounds, but has not definitely decided yet.] PPRP Proposal: The next two PPRP meetings are 28 January and 25 March 2002. The former is too early for us so we will aim to submit a proposal to the latter meeting. The usual deadline for submissions is two weeks before, which is 11 March. The Blair report has put a figure of 0.5Mpounds down for UK ECAL work over the next few years and if our proposal is around this figure, it will not be a major suprise for the PPRP. Note, travel is not included in this figure. It is important that we are sure there is no existing system from a non-running experiment which we could use, before asking for significant funds. Action: everyone should ask around about old ADC/DAQ systems; in particular Paul will ask Phil Burrows and Chris Damerall about SLD and Paul Grannis (who is visitng IC at present) about D0. The proposal will be written in latex and will need to contain the following sections; o) The physics case for the LC (straightforward) and for the high-tech Si-W ECAL (which is less straightforward). The main goal is hadronic jet resolution to separate W's and Z's, but there have been some doubts raised about whether the energy flow idea is absolutely necessary. The main aim would be to have an ECAL such that its intrinsic resolution was not a limiting factor for the jet resolution. It seems useful (essential) for a UK person to start studing these issues and David and/or Nigel said they might be interested in doing so. It was thought that Grahame Blair's BRAHMS simulation was based on GEANT3, not GEANT4. Given that a lot of reconstruction software exists for the ECAL, then it seems sensible to use the CALICE simulation. Action: Paul to forward the basic instructions he received on how to run the CALICE simulation. There should also be some reference to ECAL work going on outside Europe, but we would not be expected to have any formal collaboration with US or Asian groups. There is work going on in Oregon (David Strom) so we we need to find out where else. o) A description of the CALICE collaboration and its goals. This needs to show which groups are signed up for what tasks, what the timescales for the project are, etc. The aims of the beamtests should explicitly state that it is not known how to build this device yet and also that the cost optimisation is a major goal. o) The proposed UK involvement. This needs to include deliverables and milestones. Tactically, it seems sensible to divide the project into prototyping and production phases. Hence, as money is tight, it will be more likely we will get at least the prototype part initially and will be asked to report back after ~ one year to get the production money. The prototype phase would be ~12 to 15 months, which would be up to Mar-Jun 2003. This would not use a major part of the money but would use most of the RAL TD effort which we will need. The production phase would be for the following ~ 6 months, i.e. up to the beamtest itself. It will mainly involve manufacturing and testing multiple copies of whatever boards we have designed and so will be where most of the money is spent. The timescales here are tight and so any slippage of the schedule for the beamtest itself would help us be more credible. We will need to list the equipment cost, RAL TD effort, travel cost, and FTE's for all personnel involved (at the level of percentages of each person) as a function of time over the next three years. This particularly needs to include (virtual) RA's or other PPARC-funded posts as the PPRP will need to be able to calculate the total PPARC cost, including salaries. If this total goes over 1Mpounds, then the project cannot be approved at PPRP level but must go to the Science Committee. This should be avoided if at all possible as it would entail a lot more paperwork and a big delay. Technical discussion: The basic parameters for the system are that it will consist of 6x6 diodes per wafer, 3x3 wafers per layer and 30 layers. This gives 324 diodes per layer and 9720 diodes in total, which sets the required channel count. The front-end amplifier chip probably will have 16 channels, each with three (or more) gain stages to give the 15 bits dynamic range required. The ADC resolution needed is at least eight bits, although ten might be more comfortable. The sampling rate should be around 10-40 MHz, given that the amplifier shaping times are expected to be O(100's ns) and several samples over the pulse waveform will be needed. The beamtest beam time structure and expected trigger rate are not known. There was some concern that the small number (18) of diodes along a row compared with the much larger number (160) in the TDR means the important issues of noise and pickup down the O(1 m) cables will not be tested. This must be bought up at the Paris meeting to see if a TDR-like geometry could be assembled. The OPAL drift chamber system consisted of 80 VME crates, each containing 24 modules with 2 channels per module. This gives a total of 3840 channels. The modules contained 100 MHZ FADC's with a 6-bit non-linear reponse, equivalent to an ~8 bit dynamic range. Each channel had either a 256 or 1024 deep sample buffer. The whole system has been taken by Volker Korbel at DESY, who is working on the LC HCAL part of the beamtest. It seems this system will not be useful for us. The MINOS run control has been written by Mark Thomson and David Ward. It is in C++ and is not platform specific. It would be straightforward to adapt and can handle multi-CPU systems. It can/does use ROOT. There has been some experience of using ROOT in beamtests with LHCb and Zeus. The feedback is mainly positive and Zeus use ROOT for all their monitoring. It is possible we would want to produce data files directly in ROOT format. It was thought LabView is mainly for small systems and we would probably not use it for this beamtest. The beamtest should use both electrons and pions. It is not clear what is available; electrons up to 20 GeV might be possible at CERN or 50 GeV at DESY, but this needs clarification. Pion beams up to 100's of GeV should be available at CERN. SLAC has an electronb beam of 50 GeV but it is hard to get time on it. It is likely such high energies are not the most interesting anyway, as the majority of particles in a hadronic jet of ~100 GeV have energies of only a few GeV. The major technical questions which need to be settled are: o) Do the ADC's get placed on the front-end board, next to the front-end chip, or in the VME crate? The former is more like a final system although the latter gies a cleaner divide between the readout and the front-end chip. o) Should the readout be event-based or burst-based? TESLA has a bunch train of 1ms followed by 199ms of no beam. The idea will be to read out all data from the 1ms during the 199ms and then sort out the individual events in software. Having a burst-based system in the beamtest would be closer to this. Otherwise, we need to make a trigger also. o) Added after the meeting; the HCAL part of the beamtest will need to be coordinated with the ECAL so that the data from both systems can be merged to give complete events. This requires a common timing system, if nothing else. To what extent can we work independently on DAQ systems? We should make sure that these are on the agenda for discussion at the Paris meeting. The discussion came up with the following system as a first idea. The UK will build front-end readout boards which house the French readout chips. To enable flexibility to changing designs of this chip, the board will take the readout chip on a daughter board. The front-end board will have the ADC's, an FPGA to do data compression (thresholds and/or zero suppression), storage memory and fibre optic connections to the VME crate boards. A fibre from the crate to the front-end boards will also be needed to allow the boards to be configured. The front-end boards will buffer all data for 1ms. The non-readout parts of the boards and the diodes will be powered up only during the 1ms detection time. This involves a mixture of analog and digital on one board, which may require more care. The VME-based receiver boards then become conceptually simple, as they simply receive the data from the 1ms period down the FO link and buffer it until read out across the VME backplane. This should allow many channels per receiver card, which would mean the whole system might fit into one VME crate, which makes the DAQ much simpler. We would probably not try to get the receiver cards to write their data directly through an ethernet interface to disk; going via a VME interface to a PC would give more flexibility about the data format on disk. To clock the system and distribute timing signals for starting the 1ms data period, we will need some sort of fast control system. UCL have some experience of this from Zeus and so might be interested in contributing effort here. As this would commit the UK to building the front-end boards, it might be that we would be asked to also provide the kapton cables which go from the diodes to the front-end. There was not great enthusiasm to take this on. Each of the front-end and receiver boards would be at least 1 SY of RAL TD effort, which costs ~100kpounds/SY. Hence, easily half of the 0.5Mpounds figure could go on engineering, which would be mainly in the prototype phase. Next Meeting: UCL on Wednesday 19 December at 11.00.