Minutes of CALICE-UK Meeting, UCL, 06/03/02
===========================================
Present: Jon Butterworth, Paul Dauncey, Ian Duerdoth, Steve Hillier,
 Martin Postranecky, Mark Thomson, David Ward, Matt Warren

Minutes: Paul

Proposal discussion: Our reactions and new plans following the change to
 the VFE chip were discussed. Paul showed a few transparencies describing
 the new VFE chip and a simple readout system; see attached slides for
 details (last 4 slides).
 It would still be possible to make something more "TESLA-like" using the
 new VFE chip, but it might be significantly more expensive. The original
 inclination to do a more sophisticated readout was justified because the
 costs were likely to be similar; this is thought to not be the case now.
 A simple system to do the job would be at most 50k pounds. At this level,
 if including the HCAL readout would be technically straightforward and
 not a large extra cost, then it was thought worthwhile providing this as
 a service to the collaboration.
 Just to confuse the issue, Paul received an email from Christophe de la
 Taille, who is making the VFE chip. He asked if we wanted separate
 channel readout in addition to the multiplexed output. The feeling was
 that having to have connectors to 10k channels would be a significant
 complication and so we should stick with the multiplexed readout.


Long-term interests; While it is clearly very early to decide, it was thought
 useful to see what each group might be interested in working on longer-term,
 ignoring other constraints. Dividing the project into mechanics, silicon
 wafers, VFE chips, readout electronics (all other on-detector readout) and
 DAQ (the off-detector readout and computing), then the interests expressed
 were;
 
  Birmingham; DAQ, possibly readout also
  Manchester; Readout
  UCL; Readout, DAQ
  Cambridge; Silicon, wafers, readout
  IC; VFE chip, readout

 Several groups also expressed strong interests in software tasks, mainly
 reconstruction and algorithm development as well as simulation. In terms
 of the hardware tasks;

  Mechanics; no interest at this time
  Silicon wafers; Cambridge
  VFE chip; IC
  Readout; All groups
  DAQ; Birmingham, UCL

 It is clear that our interest (and experience) is mainly focussed in the
 readout (and also DAQ to a large extent). This would be worth flagging up
 to the PPRP. One point made was that the readout needed for the final system
 might not be well-defined for quite a while, since changes to the VFE would
 have knock-on effects which change things downstream (as we have seen
 recently). This might mean that if we did decide to go this route
 longer term, then our main intellectual input might need to be in the software
 tasks for a long time yet. It would seem sensible to put a lot of our
 effort into this area now. Given the simpler system outlined above, it
 is likely less effort is needed to get this working and so more people
 should be available for the software studies.
 
 Manchester also expressed an interest in PMT studies for the HCAL. There was
 some concern in the meeting that we were already spread thin and so taking on
 another task might be difficult. In addition, if this requires funds, then
 we would need to include something in the PPRP bid. This might be interpreted
 as a lack of focus. However, if there is any other interest in this then it
 should be considered, so people should speak up asap.


PPRP submission: We should now aim for the May 13 PPRP meeting. This means
 the submission document deadline is April 29. We should aim to have a meeting
 to finalise the draft around a week before this date and so should have a
 draft to discuss at that meeting a week before the meeting itself. 16 April
 at UCL was suggested for the date, which would mean the draft would need to
 be ready before people go to the IoP/St Malo.
 [Note added after the meeting by Paul: having forgot to bring my diary, I
 only now realise I cannot make 16 April. Can we rethink that date?]
 

Other meetings: There will be a CALICE ECAL and HCAL meeting at Paris on
 11 April, the day before the St Malo meeting starts. This will include a
 Technical Board meeting, at which Rolf Heuer will raise the issue of the
 VFE chip being changed without consultation. It would be good to get a UK
 person at that meeting; if you intend to go to the Paris meeting, can you
 contact Paul asap?
 Mark seemed to be the only person who was planning on going to St Malo.
 This meeting is in the next FY and we have probably spent most/all of
 our funds from this FY. Because we did not make it to the March PPRP
 meeting, we do not have travel funds allocated for the next FY. Paul will
 contact Ken Peach to see if some temporary cover can be arranged.


TESLA system discussion; Paul put together some numbers on how the final
 system might look; again see attached slides for details (first 8 slides).
 The critical decision for the architecture is whether the threshold cut can
 be applied to the analog data or only to the digital data. If the former,
 then a reasonable analog pipeline followed by a quite small number of
 (F)ADC's would look feasible. ATLAS have analog chips with 4-bit DAC
 settings for their thresholds, so it seems likely such a system would
 be viable.