Minutes of the CALICE-UK meeting, UCL, 22/04/02 =============================================== Present; Jon Butterworth, Paul Dauncey, Chris Hawkes, Steve Hillier, Dave Mercer, David Miller, Martin Postranecky, Mark Thomson, David Ward, Matt Warren, Nigel Watson Minutes; Paul Paris/Jussieu CALICE meeting; Nigel was the only UK person at the Jussieu meeting on 11/04/02. He had already sent round a detailed email following the meeting. The summary of the most important points was: o) The VFE chip, called FLC_PHY1, has not changed from what we expected and the effort seems better focussed on the physics prototype. The shaped peaking time is expected to be 180ns. The first prototype of the PCB which holds three silicon wafers and six VFE chips is due to be fabricated this summer. There should be no problem with us having a PCB for testing with our prototype readout boards as it would not be needed before March (and could be as late as May) next year. There is an difference in the cable signals compared to what we assumed, as they use a shift register on the VFE to drive the multiplex output. This needs to be settled asap. o) There is no progress on the test beam, with regard to defining what is needed in terms of number of events, energies, etc. Ammosov advertised the IHEP (Russia) facilities, with electrons, muons and hadrons available between 1 and 20 GeV, at rates of 1 to 1000 kHz. This would be available only in spring or autumn. o) The digital HCAL physics prototype is still quite undefined. It will have up to 38 layers, each of around 10k channels, which potentially gives up to 50kBytes/event. The tile HCAL will be between 800 and 1200 channels and so, depending on the readout arrangement, could fit into a handful of our readout boards. However, it is not yet known if this will actually be possible. The HCAL simulation shows between 6 and 8% leakage for 100 GeV pions so a tail catcher is being considered. o) There has been progress with the simulation, adding more sub-detectors and improving the event display. o) There is some optimism that silicon costs might be falling; a figure of $2/cm^2 (cf $3/cm^2 in the TDR) was mentioned. St Malo LC meeting; David Miller reported on the ECFA/DESY St Malo meeting, which was 12-15/04/02. There will be an energy flow study group and someone will be needed to run this; any UK people interested should contact him. David recommended a talk on this by Arthur Maciel (N.Illinois). The next meeting in this series will be at Prague on 1-4/11/02 with Amsterdam following in April 2003. This is nominally the last but it seems likely the series will be extended. The next worldwide LC workshop will be in Korea on 26-30/08/04 and then in Durham in spring 2004. Institute contributions; The tasks which each University might want to take on were discussed and some preliminary assignments made: o) Board layout and fabrication; it was not clear any institute would be able to do this in-house, although if the board is not too complex, IC might take it on. It was thought prudent to ask for effort from RAL TD for this for all boards. The estimate was 1 month of effort for each of the prototype readout board, production readout board, trigger board and test board. This is a total of 4 months effort. Experience of RAL drawing office has been mixed; it is important to book early to get work through in time. o) Trigger and test boards; UCL were interested in taking this on. They will have around 4 to 5 months of effort, thought to be close to what is needed, although Martin and Matt will not be available before the start of 2003. o) Readout board; Manchester are interested in the FPGA design, which is estimated to be around 3 months effort and matches well to Dave Mercer's time. Some of the board test software could also be done by them. IC would like to do the board design, estimated at 6 months effort. o) DAQ; suprisingly, no-one claimed experience of DAQ systems. IC (and possibly Birmingham depending on Steve's availability) will look into this. Cambridge could supply run control and some other online software. o) Simulation studies; Birmingham, Cambridge and Manchester will all work on this. These assignments should be regarded as preliminary until the system is fully specified, as the effort required could easily change significantly. As a precaution, it was thought prudent to ask for some additional design effort from RAL TD, in addition to the layout and fabrication effort, to supplement the above. A figure of 0.5 FTE for each of the two years was thought appropriate. Birmingham have asked for an RA in the rolling grant for LC work. Other institutes were also considering this. It seems highly unlikely these will be granted, given the present funding situation, so it was decided that we should request funds from the PPRP for these rollng grant posts as a contingency. PPRP Proposal; The draft was discussed and the following points raised: o) There was little connection between the technical problems mentioned and what would be meaured at a beam test. o) There were no details on the beam test itself, such as energies, particles, data volumes, etc. o) The UK effort on simulation studies was not mentioned; Mark and David Ward offered to supply a section on this. o) We should not include the reasons for the much-reduced cost of the bid. o) Make the HCAL discussion more positive. o) Add more to the electronics section; add another figure giving an overview and subdivide into sections on each of the three boards. o) The schedule needs to be adjusted and made more detailed. Paul will do updates and recirculate before the deadline on 29/04/03. As the talk is only 30 minutes, it was decided that Paul should do the whole talk and not try to split it between two speakers. Future meetings; We will meet after the PPRP to discuss what to do next. This will be at 1pm at UCL on 20/05/02. There will be a general CALICE meeting in October this year. It is not known when or where the next CALICE-ECAL meeting will be.