123456789012345678901234567890123456789012345678901234567890123456789012 MAPS Sensor PCB Layout Review, RAL, 26/06/07 ============================================ Present: Jamie Crooks, Paul Dauncey, Matt Noy, Vladimir Rajovic, Konstantin Stefanov, By phone: Marcel Stanitzki Minutes: Paul Schematics: Vladimir went through changes to the schematics since the schematics review on 17/05/07. Pgs 1 and 2: A temperature sensor has been added and is read out using the SPI bus. It will measure the temperature of the PCB and so (since PCBs are good heat conductors) will give a good reflection of the sensor temperature. It has an LSB of 1C. An additional four LVDS inputs have been added to allow each of the components on the SPI bus (including the above temperature sensor) to be individually addressed. Hence, each can be loaded and read back independently of the others. Six LVDS outputs have been added. They are connected directly to a dip switch so that a 0-63 board (and hence sensor) id value can be set and read out. This will simplify book-keeping. These changes have resulted in a total of 68 LVDS inputs (plus one loopback input) and 48 LVDS outputs (plus one loopback output). The 68 inputs are 61 for the sensor and the other 7 for the SPI. There are 51 sensor outputs but not all are transfered to the USB_DAQ. The previous number was 45 but these had to be reduced to make room for the id lines. Now, a total of 41 sensor outputs are sent out, with the other 7 being the 6 id lines and 1 SPI output line. The four sensor lines no longer sent are the DEBUG_HIT600, DEBUG_HIT200, DEBUG_HITOUT1 and DEBUG_HITOUT2, none of which are required for operating the sensor. Pg 3: This page has been corrected for the issues raised by Jamie in the previous schematics review. Putting PU to VDD (as done for the one of the four DACs) will set the output to the top of the range. This is 1.65V (i.e. 3.3V/2) at the DAC output and 1.8V at the output of the networks. This is intended to be set for one side of the threshold differential pair so as to give a high threshold, rather than the same value for the differential and hence zero threshold. However, this is currently hardwired; for flexibility, a zero ohm resistor should be added between PU and VDD so that it could be removed if needed later. Pads to allow the resistor to be connected to VDD or GND (or neither) should be added. Leaving PU floating (as it done for the other three of the four DACs) will give the mid-range value at power-up, i.e. 0.9V at the network output. Pg 7: The jumper for the substrate has been added, to allow it to be connected to either the analogue or digital ground, or be left floating. There are more decoupling capacitors on the power supplies than are needed (and than fit on the layout) so some will be removed. Currently there are four capacitors per net; two or three should be sufficient. Pg 8: The six amplifiers and coaxial cables have been added since the previous review, as requested. The amplifiers allow rail-to-rail output. The feedback capacitors may need to be adjusted. Pg 9: The logic analyser headers have also been added as requested in the previous review. Pg 13: The 6-bit dip switch and temperature sensor are both new and were discussed above. Layout: Issues raised during the layout discussion are listed below. The mechanical holes do not have sufficient clearance. There needs to be clearance around the hold, approximately to double the hole diameter, to allow for the screw head. In addition, there needs to be sufficient clearance from traces such that the hole drill will not cut or short out the traces. The screw holes will be reduced from M3 to M2 to help satisfy these requirements. The hole for laser access to the test structure is currently 0.7mm wide, i.e. a 0.4mm hole made with a 0.3mm drill bit. The tolerance for gluing the sensor onto the PCB may not be much better than this and it was thought prudent to have a larger hole. The hole will be doubled to 0.8mm, giving a total width of 1.1mm. When gluing, then no glue should be put close to the hole or it could cover it over. The region for glue is 1mm wide around the circumference of the sensor. The glue will be conductive to allow a contact to the silion bulk. However, it was not clear if this contact would have a significant resistance. This could be measured with a mounted sensor using an epitaxial layer ground contact and the substrate contact. The blue block on the top surface is for a sticky label for board identification. The PCB will probably be single-sided although the cost should not be a major issue so e.g. decoupling capacitors could be added to the underside to help with the remaining layout. The total size of the PCB will be 205mm x 105mm. This fits onto the laser mount. A support jig for wire-bonding the sensor will be needed. This will use the mechanical holes to support the PCB so the same screw head stay-clear is required on both sides of the PCB. The PCB will have 8 layers; four for signal routing and four for power and ground planes. The digital ground will cover the whole plane while the analogue ground will only connect the sensor area and the regulator. The drive strength was raised, both of the sensor and the LVDS receivers which have to drive the traces along the board. The average is ~15cm long but the maximum is 29cm. It was thought in both cases there would be sufficient drive strength. There is no known bump-bonding process which can easily bond to the 60um sensor pads. If a process was found, then it would need to be done to a small adapter PCB which would then be wire-bonded to the top of the sensor PCB. To fit the pads to wire-bond to onto the sensor PCB would be difficult given the current layout. Hence, it was decided this should not be done and that bump-bonding the first sensor (at least to use with the sensor PCB) will not be done. A diode to drop from the 5V input to around 3.9V for the regulator will need to be added. Schedule: The aim is to complete the layout and submit it by Wed 3 July. Three PCBs will be fabricated with a three-day turnaround and so should be available by Tue 10 July. The other twelve (of an initial batch of fifteen) will be made when the first set are tested. The component population of the first three will be done commercially. This can be done on a five-day turnaround, meaning they are available by Tue 17 July. These must then be tested for shorts, etc, as well as DAC and temperature functionality before gluing on sensors. We should always keep a PCB with no sensor so only two of these first three will have a sensor attached. The testing should be completed within a week either using the USB_DAQ or the RAL/PPD NI board to control the SPI interface. The remaining twelve sensor PCBs should be submitted for manufacture with a two or three week turnaround by the end of July, so they will be ready and populated by the end of August.