MASTER_CONTROLLER Project Status
Project File:	master_controller.ise	Current State:	Programming File Generated
Module Name:	top_master_controller	Errors:	No Errors
Target Device:	xc3s1000-5fg676	Warnings:	445 Warnings
Product Version:	ISE 9.2.04i	Updated:	Tue Jul 21 16:11:17 2009

 

MASTER_CONTROLLER Partition Summary

No partition information was found.

 

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	2,009	15,360	13%
Number used as Flip Flops	2,007
Number used as Latches	2
Number of 4 input LUTs	2,300	15,360	14%
Logic Distribution
Number of occupied Slices	1,998	7,680	26%
Number of Slices containing only related logic	1,998	1,998	100%
Number of Slices containing unrelated logic	0	1,998	0%
Total Number of 4 input LUTs	2,533	15,360	16%
Number used as logic	2,300
Number used as a route-thru	232
Number used as Shift registers	1
Number of bonded IOBs	108	391	27%
IOB Flip Flops	7
IOB Master Pads	8
IOB Slave Pads	8
IOB Dual-Data Rate Flops	16
Number of Block RAMs	10	24	41%
Number of GCLKs	4	8	50%
Number of DCMs	2	4	50%
Total equivalent gate count for design	702,875
Additional JTAG gate count for IOBs	5,184

 

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Jul 21 16:08:39 2009	0	434 Warnings	42 Infos
Translation Report	Current	Tue Jul 21 16:08:49 2009	0	0	2 Infos
Map Report	Current	Tue Jul 21 16:10:17 2009	0	4 Warnings	6 Infos
Place and Route Report	Current	Tue Jul 21 16:10:49 2009	0	5 Warnings	1 Info
Static Timing Report	Current	Tue Jul 21 16:10:58 2009	0	0	2 Infos
Bitgen Report	Current	Tue Jul 21 16:11:16 2009	0	2 Warnings	0