# //  ModelSim SE 6.2f Jan 13 2007 Linux 2.6.18-1.2798.fc6
# //
# //  Copyright 1991-2007 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading project work
# Compile of simple_trigger_input_latch_v0.vhd failed with 1 errors.
# Compile of simple_trigger_input_latch_v0.vhd was successful.
vsim -coverage work.simple_trigger_input_latch
# vsim -coverage work.simple_trigger_input_latch 
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: [1] (vopt-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
# Loading /home/matt/usr/HDL/modeltech/linux/../std.standard
# Loading /home/matt/usr/HDL/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /home/matt/usr/HDL/modeltech/linux/../ieee.std_logic_arith(body)
# Loading /home/matt/usr/HDL/modeltech/linux/../ieee.std_logic_unsigned(body)
# Loading work.simple_trigger_input_latch(v0)
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__0  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__1  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__2  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__3  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__4  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__5  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__6  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__7  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
vmap unisim /home/matt/vhdl/shared_libraries/unisim/work
# Modifying /home/matt/project/calice/master_controller/work.mpf
vmap simprim /home/matt/vhdl/shared_libraries/simprim/work
# Modifying /home/matt/project/calice/master_controller/work.mpf
vmap xilinxcorelib /home/matt/vhdl/shared_libraries/xilinxcorelib/work
# Modifying /home/matt/project/calice/master_controller/work.mpf
vsim -coverage work.simple_trigger_input_latch
# vsim -coverage work.simple_trigger_input_latch 
# Loading /home/matt/usr/HDL/modeltech/linux/../std.standard
# Loading /home/matt/usr/HDL/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /home/matt/usr/HDL/modeltech/linux/../ieee.std_logic_arith(body)
# Loading /home/matt/usr/HDL/modeltech/linux/../ieee.std_logic_unsigned(body)
# Loading work.simple_trigger_input_latch(v0)
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__0  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__1  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__2  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__3  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__4  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__5  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__6  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
# ** Warning: (vsim-3473) Component instance "u_ibufds_lvds_25 : ibufds_lvds_25" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /simple_trigger_input_latch/u_gen_ibufds_lvds_25__7  File: /home/matt/project/calice/master_controller/src/simple_trigger_input_latch_v0.vhd
view wave
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
force -freeze sim:/simple_trigger_input_latch/clk 1 0, 0 {12 ns} -r 25ns
force srst 1
run 100ns
force enable 0000000000000000
force invert_mask 0000000000000000
force trig_in_se 0000000000000000
# Value length (16) does not equal array index length (8).
# 
# ** Error: (vsim-4011) Invalid force value: 0000000000000000.
# 
force invert_mask 00000000
# Value length (8) does not equal array index length (16).
# 
# ** Error: (vsim-4011) Invalid force value: 00000000.
# 
force invert_mask 0000000
# Value length (7) does not equal array index length (16).
# 
# ** Error: (vsim-4011) Invalid force value: 0000000.
# 
force trig_in_se 00000000
force trig_in_p 00000000
force trig_in_n 11111111
run 100ns
force srst 0
run 100ns
run 100ns
run 100ns
force trig_in_se 00000001
run 50ns 
force trig_in_se 00000000
run 100ns 
force enable 0000000011111111
force trig_in_se 00000001
run 50ns 
force trig_in_se 00000000
run 100ns
run 100n s
# Invalid time value: 100n s
run 100ns
force srst 1
run 25ns
force srst 0
run 100ns
