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MAPS USB_DAQ Adapter PCB Review, RAL, 26/06/07
==============================================
Present: Jamie Crooks, Paul Dauncey, Matt Noy, Vladimir Rajovic,
 Konstantin Stefanov,

Minutes: Paul


Presentation: Matt went through an overview of the board schematics and
 layout; see slides on review web page. The items raised for discussion
 are listed below.


Items discussed: The board currently has 65 LVDS signals going upstream
 (i.e. to the sensor PCB) and 49 downstream (i.e. from the sensor PCB).
 The 65 are 64 for the sensor PCB and 1 loopback to measure the cable
 delay. Similarly, the 49 are 48 sensor PCB signals and the 1 loopback
 line. The loopback path does not go through the LVDS receivers and
 transmitters on the sensor PCB.

 The adapter board will include a hex switch to allow the different
 boards in a system to be separately identified as the hex setting will
 be part of the USB PID value. A particular hex value will also be used
 to identify the master USB board, with other values being used for the
 slave boards. Hence, there will be no requirement to select the master
 or slave boards through software. As the cabling of the clock and data
 are not common to master or slave, then software selection would in
 any case be meaningless.

 The master board will fan out the clock to up to four slaves. There are
 also two LVDS lines each way to each slave. These latter will allow
 synchronous bunch train start signals to all boards and also bunch
 train veto signals from each slave back to the master.

 The master-slave data connections will need a specially built cable to
 get the polarities and orientation correct. It would be useful if this
 could have a connector which can only be inserted the correct way.

 The clock skew over the master-slave cable will be ~1ns and the
 components may add another ~1ns. It would be possible to make the clock
 distribution cable take the clock out and feed it back into the master
 so they have the same cable length (and hence clock phase) as the
 slaves.

 The USB_DAQ has internal 40MHz and 100MHz clocks. We will use the
 100MHz for the MAPS work. There is no known requirement for any clock
 edge which must be other than a multiple of 10ns.

 The USB_DAQ firmware code is loaded on power-up or reset from an
 on-board EPROM. This can be reprogrammed using a JTAG cable. The JTAG
 connector is on the part of the USB_DAQ board which is not covered by
 the adapter board and hence reprogramming can be done with the adapter
 board in place. The USB_DAQ hardware also supports FPGA (
CHECK and EPROM?) 
 reprogramming through USB although the firmware to support this does
 not yet exist.

 The PMT input signals may be shorter than the 10ns clock sampling time.
 The circuit includes a latch signal to allow the short input signals
 to set a latch or not. If not, the FPGA can sample the signal
 asynchronously and latch it internally. In either case, the latch
 should be cleared after it is sampled.

 The adapter PCB will not be easy to get on and off the USB_DAQ, given
 the number of connector pins. In most cases, they should be considered
 to be an single unit once assembled. The FPGA will not have a good air
 flow unless a fan is positioned to blow air between the two boards.
 However, this was not thought to be a problem as the FPGA should not
 generate a lot of heat. The only adjustable components between the
 two boars which will not be accessible are the USB_DAQ power regulator
 jumpers, which probably should not be changed once set in any case.

 The PCB will have four layers and will be double-sided. Clearance
 between the two boards is not a constraint.

 The connectors to the sensor PCB are male on both boards so the cables
 will have female connectors at both ends. This is to allow the cable
 loop-back test of the adapter board, where a cable is inserted between
 the upstream to downstream connector.

 The grounds for the adapter and sensor PCBs will be separate.

 The laser hardware interface is currently assumed to use TTL. However,
 this couples the grounds of the two systems together and so may give
 problems. The fallback is to convert the signals to LVDS at the laser
 and then use the slave inputs and outputs. This should not be an issue
 as the laser setup is not foreseen to operate more than one sensor at
 a time. A software switch would be needed to select what the slave
 I/Os should be used for.


Changes: The sensor PCB recently added a further 4 input LVDS signals
 to allow the SPI DACs to be individually addressable, so the total is
 now 68 inputs, or 69 including the loopback. Hence, a further four
 upstream signals must be added to the adapter board. This will require
 another LVDS transmitter component on the adapter board; in fact, an
 8-channel component will be added and six
(CHECK!)
 of these eight lines will be added to fill the connector.

 The adapter board currently regulates 5V to 4V for use by the sensor
 PCB. However, the sensor PCB will use a series diode to reduce 5V to
 ~4.3V and so would not need regulation on the adapter PCB. Hence, the
 regulator circuit should be removed.

 A push-button will be added to give a full board reset, including a
 reload of the firmware from the on-board EPROM.

 The PMT input amplifier and discriminator circuit needs further work.
 The current schematics have the two channels wired differently and
 IC13 is incorrect for the current design, although both will be
 changed. The issues are to get a local current return path for the
 PMT signal while handling the negative polarity signal. In addition,
 various PMTs may have a significant difference in signal size so a
 variable gain range might be useful, if straightforward to do. A final
 circuit design was not determined during the review.

 Although there is no specific known requirement, it was thought prudent
 to add some direct LVDS inputs and outputs to the FPGA. A new header
 which connects to the unused pins on the USB_DAQ-adapter connectors
 will be added, probably in the space freed up by removing the power
 regulator.


Schedule: The main remaining items are the extra LVDS outputs and the
 PMT input circuit. Matt estimates these can be completed by the time
 he leaves on a trip next Wed 4 July.

 With a three working day turnaround for fabrication of two boards,
 then they would be returned by Tue 10 July. These could then be
 populated (at Imperial) by Thu 12 July. These would be used by Jamie
 and the laser test stand.

 The remaining eight adapter boards could be fabricated when the first
 two have been checked, by around the end of July. These could be done
 with a two week turnaround, being returned by mid August. The assembly
 would then be done in the last two weeks of August, meaning that these
 remaining boards would be ready by the end of August. This is
 compatible with the schedule for the source and cosmics tests as it
 will take several weeks for Jamie to have studied the sensor and
 determined a reasonable set of operating parameters.

 There are two USB_DAQ V1 boards ready. The V2 PCB has fixed a few
 minor issues and ten of these have been fabricated and are in hand.
 Matt will get four of these populated commercially straight away, with
 the other six being populated at Imperial when technical effort
 becomes available. The first four should then be ready well before the
 first two adapter boards. The remaining six should also be complete in
 time for the other eight adapter boards.

 The firmware still needs some work and Matt estimates a first working
 version with the necessary basic functionality should be ready by mid
 July, in time for the first PCBs on the above schedule.


[Note added after the review: An inconsistency was found in the signal
 order on the middle of the three USB_DAQ adapter/sensor PCB cable
 connectors. This is the connector which has both input and output
 signals and the two layouts had the input and output signals at
 opposite ends. This has been fixed by changes at the USB_DAQ adapter
 end.]