CALICE MAPS Final Design Review 1, Part 1, RAL, 28/02/07 ======================================================== Present: Jamie Crooks, Paul Dauncey, Nicola Guerrini, Matt Noy, Mark Prydderch, Marcel Stanitzki, Konstantin Stefanov, Mike Tyndel, Renato Turchetta, Giulio Villani Minutes: Paul Sensor simulation: Giulio showed some results on the charge collection with the latest layout, see the FDR web page. The layout he used had the deep p-well only extending 0.5mu outside the n-well areas (the minimum allowed by the foundry design rules) rather than the 2-3mu suggested previously. He simulated the charge collection both with and without a 3mu guard ring (i.e. +/-1.5mu either side of the pixel boundary) around the outside of the pixel. Again this is the minimum width of deep p-well allowed. The diodes were placed 9mu from the edges. The charge collected from the edge centre is reasonable and so putting the n-wells out at the sides does not seem to have degraded the efficiency there to a significant effect. However, the charge collection at the corner is still very marginal, with only 260e- (out of a maximum of 1350e-/4 ~ 340e-) collected in each pixel. This makes the signal effectively at the threshold level given the noise values (and hence threshold) expected. The impact of the diode size should be simulated again asap (i.e. before the next meeting on Wed 7 Mar) to check whether the signal and noise decrease for 1.8mu (or even 0.9mu) diodes would improve the S/N ratio or not. Very little difference with and without the guard ring was seen, so it seems any effect is small. However a charge deposit just within the guard ring would be most sensitive and so this should be simulated to check for any difference. However, this is less critical than the diode size study, above. Pixels: Renato described the changes since the IDR and then the layout was reviewed. Changes: These are mainly described in the FDR pixel document, see web site. The diodes have been increased from 1.8mu to 3.6mu, which has led to an increase in noise for the sampler circuit from 27e- to 42e-. This does not include the comparator noise, which is around 12e- to be added in quadrature. The total noise is likely to be above 50e-, which makes the corner charge collection less than 5sigma. The capacitors planned at the time of the IDR were MIMCAPS, but these can only use the top metal layers. It had been planned to use the routing metal layers to provide parasitic capacitance but although this was previously said to be essential, it has now been dropped so only n-well capacitors will be used. (This means there is one variant now free, which could be used for with/without guard ring or for two diode sizes.) The n-well capacitors show results in the simulation which depend on their polarity; changing the orientation of one capacitor around seems to reduce the noise by 20e- and this effect is not understood but should be before submission. Mark said they had successfully used this capacitor technology before. The input line to the comparator could move to sit at a level where current flows from power to ground through the comparator; this issue should be evaluated and corrected if necessary. The expected power per pixel when running continuously is 8-10uW or ~4mW/mm^2. With a 1% ILC duty factor, this would be 40uW/mm^2. As most power is supplied via 1.8V, this corresponds to a continuous current of ~5uA/pixel. Layout: There are six metal layers. The lowest two (M1 and M2) are mainly used for signal routing. M3 is little used but contains some power lines. M4 is used for power and bias distribution. M5 is almost entirely used for tracking the pixel output signals to the logic columns while M6 (which is thicker and hence has less resistance) is used for power distribution. Many of these layers cover a significant fraction of the surface and so there are very few gaps through all six layers where light would be able to reach the silicon. It will therefore be necessary for the laser to be shone on the rear surface of the sensor and hence it is important than the foundry does not put a metalisation layer on the substrate. The diodes are connected by an interconnect which is ~75mu long. This gives a parasitic capacitance of 14fF, compared with the 8fF assumed at the IDR. (The difference between 1.8mu and 3.6mu diodes is equivalent to around 17fF in terms of input capacitance.) This increase clearly directly affects the noise and should be reduced if possible. The metal line has a ground shield 0.5mu away on both sides, which gives a major part of the capacitance. This should be moved further out where possible and also the metal line could be narrowed. However, it already has a resistance of around 20ohm so narrowing could cause problems. The foundry normally requires a minimum fraction of a metal layer be filled and this design rule is currently violated. They recommend filling in unused areas with metal but this would contribute to the parasitic capacitance and so will not be done in this design. The comparator input and output metal lines cross over each other at one point. Although the capacitive coupling will be small, the effect of any feedback should be simulated to be sure this will not cause problems. Renato will reroute the lines a little to reduce any effect in any case. The power supplies for the monostables currently are shared with the logic column circuitry and so there is potentially a problem that many monostables firing at once would cause the supply to droop and hence corrupt the sensor memory. They should therefore be supplied with a separate power supply. Also, there should be no ground connections to the substrate from the monostables, to ensure the current return path is only via the metal layers. There are two main changes for the shaper circuit compared to the sampler. Firstly, only one monostable is needed; what is done with the other depends on whether the sensor is being optimised for S/N or to compare the two pixel types. To get the highest signal, then clearly the monostable would be removed so there is no absorbtion of charge by its n-wells. However, this will make comparison of the sampler and shaper more difficult. It was decided that it should be left in place and be powered so it absorbs the same amount of charge in both pixel types. This is then the minimum layout change also. The second change is to the analogue circuit within the C-shaped capacitor bank. The current schematics (and hence simulations) include a capacitor which cannot fit into the available space. The common layout will not be changed, but the capacitors will be strunk to fit into the space available. This will potentially give a larger mismatch. Logic: Jamie described the changes since the IDR and then the layout was reviewed. Changes: These are mainly described in the FDR logic document, see web site. The logic column configuration simulation has the data emerging two clock periods later than expected. This would not be harmful in reality as an offset could be added during readout but the cause should be understood in case it relates to a deeper problem. Layout: All routing is on M1-3, with M4 being used for power. There is very little on M5, which is where all the incoming signals from the pixels are tracked to the logic. The logic column will now occupy five pixels rather than the four expected. This clearly increases the dead area of the pixel. Ideally, the logic column would mimic the charge absorption of the active pixels so the pixels next to the column act like all the others. However, this would be very difficult to achieve; the realistic choices are to add a lot of deep p-well under the logic components (to reduce the absorbed charge as much as possible) or to leave it out (to absorb as much charge as possible). Konstantin had previously shown an example where non-absorbed charge had caused problems, so the former was not considered a good option. This means that the neighbouring pixels to the logic could be less efficient that normal; a loss of 25% per pixel might be expected, increasing the effective dead area to 5.5 pixels equivalent. There is also a one-pixel wide gap between the two active areas of pixels in the horizontal direction to allow buffer drivers for the logic columns. The active area (including the logic) is 9.40mmx8.45mm (see below). Within this area there will be an effective dead area of 4x5.5x50mux8.4mm for the logic columns plus 50mux9.4mm for this horizontal dead strip between the two vertical arrays. This gives a dead area of over 12%. Including the region around the active area, over the total pixel size of 10mmx10mm, the dead area is 30%. Both these figures ignor any inefficiency within the pixels, i.e. for particles near the corners. There is an "antenna" design rule limiting the length of metal traces, to reduce the danger of static buildup during manufacturing from damaging the devices. The exact length allowed was not known but Jamie thought it was likely he had violated this rule. The best cure is to add a diode in parallel every so often as needed to limit the total unprotected length of each metal section. Global: This has not been laid out yet and so the review could not be done, although some items were discussed. Bonding pads: It is thought essential for the eventual ILC use that the sensors are assembled to PCBs using some flip-chip bonding, rather than wire bonds, so as to keep the distance between sensors as small as possible. There will not be time to put down pads which would be large enough to test various bonding technologies, although this was specified as a requirement. There will be around 200 I/O pads around the 4cm outer edge of the sensor. Each will occupy 150mu of the perimeter and extend inwards by 250mu, although the bond pad itself will be 60x60mu^2. Konstantin stated this would be within the specifications for solder bump-bonding, but probably not for gold bonding. It was not known how large pads would have to be for gold. The ATLAS solder bump-bonding cost is 1keuro/wafer although there would be some non-negligible overhead for masks and setup. Test structures: Various test structures would be desirable but are a low priority and should be dropped if there is no time to lay them out. Several arrays (3x3 or 5x3) of pixels would be useful, with direct outputs from the amplifiers, comparators and monostables tracked to external pins. These would be needed for each of the four variants. Also some flip-chip test bonding pads might be useful although a full characterisation of the technology would require hundreds of bond pads to measure the failure rates and bond resistances in a meaningful way. Power: Most of the core of the sensor runs at 1.8V. There are some components (for reset and SRAM write) which require 3.3V. The I/O is powered separately and can be run at either 1.8V or 2.5V, whichever is convenient. The I/O will be connected straight to an LVDS converter so this component will probably specify which is used. Area: The active plus logic area is (42+5)x4x50mu = 9.40mm horizontally and (42x4+1)x50mu = 8.45mm vertically. The I/O pads will occupy 250mu along each side, leaving a distance of 0.10mm total at the sides and 1.05mm total at the top and bottom. Hence, the test structure need to fit into this ~1mm above or below the sensitive area. Discussion: It is clear the design is not complete and it will be extremely tight to finish it by March 12. There are various items noted above which should be studied but it is unlikely there will be time available for this. Hence, there is some risk in submitting the design before it is fully understood; this needs to be balanced against the consequences of having a non-functional sensor from this fabrication. The external referees considered that the highest priority should be to send a preliminary design to the foundry asap so as to check that there are no technical issues for submission. This will be the minimum (but complete) sensor, i.e. no test structures and a single variant. This should be done by the end of the week to have any chance of reacting to problems found in time. The foundry was sent a preliminary pixel layout a week ago for them to review but there has been no response so far; they should be pushed as this is in important check. Effectively the FDR will need to be finished during the next MAPS meeting at RAL, on Wed 7 Mar. [Note added after the meeting: Part 2 of the FDR will be held on Fri 30 Mar.]