CALICE MAPS Final Design Review 1, Part 2, RAL, 30/03/07 ======================================================== Present: Jamie Crooks, Paul Dauncey, Nicola Guerrini, Mark Prydderch, Marcel Stanitzki, Renato Turchetta Minutes: Paul Sensor simulations: Giulio had distributed simulation results on the S/N for various diode sizes before the review. His conclusion is that 1.8um diodes give better S/N values than either 0.9um or 3.6um. The optimal value appears to be between 0.9um and 1.8um but no simulations have been done between these points. Hence, the sensor will be made with 1.8um diodes. N-well capacitors: A different capacitance is seen for the n-well capacitors (used in both the sampler and shaper), depending on their polarity. All combinations of polarity were simulated to determine the optimal S/N combination. For the sampler, there are three capacitors and hence eight combinations; the noise for these is shown in the xls file on the FDR web page. For the 3.6um diode size, Eldo and Spectre give S/N results which differ by around a factor of two but the dependence of the S/N of the polarity combination is reasonably consistent between the two. Note, Giulio's values of S/N use the lower (Eldo) noise value and so are potentially on the optimistic side. Spectre cannot simulate combinations where the internal node is floating and so is missing some values. For 3.6mu diodes, the best value is the "BTTBTB" combination with the "BTBTTB" combination (which reverses the polarity of the middle capacitor) being close, although this is one for which the Spectre result is missing. The best value for 1.8um diodes (for which only Spectre results are available) is again given by the "BTTBTB" combination and so it was assumed the "BTBTTB" combination would also be good. These two will be implemented as the two variants for the sampler. For the shaper, there is a fourth capacitor for the shaper feedback. Only Spectre results are available; see ppt file on the FDR web page. The optimal value for the same three capactors as for the sampler case is given by the "TBBTBT" combination and the equivalent combination with the middle capacitor inverted, "TBBTTB", is assumed to be next, although again this cannot be simulated by Spectre. The fourth capacitor using here will be set to "TB" in both cases. Note, the polarity combinations for the two cases are labelled in opposite order in these files. Pre-shaper layout: The main changes compared with the sampler case are the removal of the second monostable and the changes to the central area. The monostable has been replaced by a 4Mohm resistor. The remaining monostable is identical in terms of n-well layout to the sampler case and so should have the same charge absorption in this region. The changes in the central area are quite substantial. One issue raised in the layout was that the capacitor mid-point crosses the shaper output and so could cause some signal degradation. This may be able to be avoided with some movement of the layout. The shaper "gain" is 120uV at the comparator input per e- input. This gives a 30mV signal for a corner nomimal minimum MIP signal of 250e-. The equivalent numbers for the sampler are 460uV/e- giving an 114mV signal for this input signal. Deep p-well layout: This is still to be done but the basic requirements are that it should be symmetric around the centre and the same for the shaper and sampler variants. The deep p-well area should extend beyond the n-well diodes by around 2um, rather than the 0.5um minimum. The deep p-well could be laid out as a cross or as a central square with four disconnected rectangles. However, the 2um spacing means the latter is unlikely to fit, so a cross was agreed. There will be no deep p-well under the five-pixel-wide vertical logic column or under the one-pixel-wide horizontal bias distribution strip. Both these will give inefficient regions and probably edge effects to the neighbouring pixels, but this seems unavoidable. Pre-sampler test pixels: The total sensor size will be 10.4 x 9.6mm^2 which leaves only a few 100um top and bottom for the test structures. The schematics for the pixel test structures were not reviewed as the layout is not yet complete. There will be several 3x3 arrays of test pixels with the central one having the most signals routed to I/O pads. There will be at least two such arrays, one for the sampler and one for the shaper, with the optimal capacitor combination used for each. The test pixels will have a threshold voltage independent of the rest of the sensor and so it can be adjusted easily. Hence, the threshold trim bits can be wired to fixed values if there are not enough bonding pads. Routing the internal signals to the bonding pads clearly adds capacitance to the nodes but these will be after the sampler and so should not affect the noise very greatly. The other eight neighbour test pixels around the centre will not have signals routed out, except one will have the monostable input and output routed out. This will allow both measurements of the monostable pulse length and also will enable the monostable to be forced to fire when studying the central pixel. Although only the schematics for the sampler case were available, the same structures are intended for the shaper. These test structures, while useful, are the lowest priority and will only be implemented when all other parts of the sensor are complete. There will be no test pads for bump/solder bonding. Connectivity can be tested by bonding to two common power pads, which are internally connected on the sensor. Top level layout and power: Jamie has not made an estimate of the digital power; this should be small compared to the pixel power but it should be estimated. Jamie has had to implement custom bonding pads as the foundry standard ones were too small. These may have a larger RC time constant which might become comparable to the bunch crossing clock of 6MHz; this should be estimated. There should be no issue with voltage drop across the bias lines as there is no standing current. Most metal layers are quite full and should pass the density rules. The exception is M3, for which metal may need to be added. Issues raised in FDR Part 1: The issues raised and recorded in the notes from Part 1 of the FDR were discussed: o "The input line to the comparator could move to sit at a level where current flows from power to ground through the comparator; this issue should be evaluated and corrected if necessary." This has not yet been done. o "It will therefore be necessary for the laser to be shone on the rear surface of the sensor and hence it is important than the foundry does not put a metalisation layer on the substrate." This has not been checked but should be straightforward to ask the foundry. o "The [diode] metal line has a ground shield 0.5mu away on both sides, which gives a major part of the capacitance. This should be moved further out where possible and also the metal line could be narrowed." There is very limited room for movement and it was found to have an effect of around 2%; hence it was not considered the effort required to change the layout. The line already has 20ohm resistance and narrowing it might cause problems. o "The comparator input and output metal lines cross over each other at one point. Although the capacitive coupling will be small, the effect of any feedback should be simulated to be sure this will not cause problems." The points at which the cross-over track changes metal layers have been moved further from the crossed track to reduce any coupling. o "The power supplies for the monostables currently are shared with the logic column circuitry and so there is potentially a problem that many monostables firing at once would cause the supply to droop and hence corrupt the sensor memory. They should therefore be supplied with a separate power supply. Also, there should be no ground connections to the substrate from the monostables, to ensure the current return path is only via the metal layers." This has been implemented. o "The logic column configuration simulation has the data emerging two clock periods later than expected. This would not be harmful in reality as an offset could be added during readout but the cause should be understood in case it relates to a deeper problem." This has not yet been done but as it is thought not to be a fatal problem, it will be tackled with a lower priority. o "There is an "antenna" design rule limiting the length of metal traces, to reduce the danger of static buildup during manufacturing from damaging the devices. [] The best cure is to add a diode in parallel every so often as needed to limit the total unprotected length of each metal section." This has not been done but the design will be sent to the foundry and they will make a recommendation on this. Discussion with foundry: Jamie reported on some information from the foundry. There will be five wafer splits over variations on the epitaxial thickness of 5um or 12um and over no deep p-well, standard deep p-well and high doping density deep p-well. The depth of the deep p-well will be 2-3um in both cases. There will be 12 wafers total, with each holding 20 sensors, distributed as: No DPW Std DPW DPW+ Epitaxial thickness 5um 0 2 2 12um 2 3 3 The foundry reviewed the preliminary pixel layout sent several weeks ago and gave some useful comments. This was largely a consistency check although they raised the issue of pixel cross-talk and informed Jamie that he was using an old version of the bonding pad library. The foundry also recommended submitting the design for a dry run. Jamie will attempt to do this today as he is not in work again until Tue 10 Apr. The current design is missing the test structure pixels and any test bump bonding pads. For technical reasons, he has also not been able to run the standard DRC check on the complete sensor. However, the dry run would see how quickly the foundry will respond, would run a DRC check, and also will give valuable feedback in advance of the real submission, which should happen soon after the next MAPS meeting on Mon 16 Apr.