CALICE MAPS Final Design Review 2, RAL, 13/06/08 ================================================ Present: Jamie Crooks, Paul Dauncey, Matt Noy, Mark Prydderch, Marcel Stanitzki, Renato Turchetta, Mike Tyndel Minutes: Paul Fabrication cost: Renato showed some slides on the likely costs for the fabrication run, see FDR2 web page. The total cost will be 41.5k for one split (three wafers) and then 3k per extra split. We had previously decided on five splits total; two of the standard wafers. In addition, the high-resistivity epitaxial layer wafers will be 4.5k for the minimum order of 100 wafers. The total is therefore 58k; this is well above the available budget so CALICE will pay 45k and CFI 13k. The unused 97 hi-res wafers would in principle be available for use in a future sensor although it was not known if they will age. Renato currently has been discussing hi-res wafers with an 18mu thick epitaxial layer. However, to aid comparisons, it would be best to keep the epitaxial layer the same as for the standard wafers, i.e. 12mu. The target is for tapeout on July 17. Pixel design: The main changes are summarised on page 2 of the support document. The main changes to the shaper pixel are to the trims and resistor. In particular, the analogue central square circuitry has not been touched. The trim LSB size is set externally. The new trim transistors correspond to x1 and x32, hence the total area relative to the previous transitors is only a factor of two, not four. The monostable layout was changed to separate the comparator and monostable power supplies. The changes to the signal diode guard rings have resulted in a ~6% increase in the diode capacitance and hence presumably input noise. The rerouted diode metal lines could be adjusted to enter the diode from the side rather than the corner which might reduce the capacitance slightly. The deep p-well region has been increased in size to be 2mu from the edge of the diode. It is also 2mu from the edge of the nearest n-well. It could be beneficial to have a "no p-well" region around the diodes. This was thought not worth implementing in this sensor but a test structure of such a diode would be interesting. It was decided that the bulk pixels should be uniform and not have both of the two capacitor variants used previously. Measurements (albeit with small statistics) indicate that Quad1 has higher gain and noise but that both Quad0 and Quad1 have equivalent S/N. Because of the noise downstream of the amplifier, it was decided to go with the variant with the higher gain, i.e. Quad1. This is the shaper quadrant with high row numbers and is in the opposite corner to the test pixels. Problem report 4: This is also discussed on pages 3-4 of the support document. The final resistor layout should be copied to a test structure so that the actual resistance can be measured directly. Similarly the capacitor design should be duplicated as a stand-alone test structure also. The decrease of S/N predicted with the smaller gain resulting from the smaller resistance implies the input noise is not completely dominant. The source of the other noise is not understood. The gain is determined by the RC value; in principle a lower R could be compensated by a higher C but this would involve changing the central analogue square circuitry. This was thought to be too risky. The layout already uses the highest polysilicon resistivity available. A significant gain variation has been seen and this could be due to not following the resistor design recommendations in terms of the trace width. However, the pedestal variations could arise from multiple sources and are not necessarily related to resistor differences; one indicator of this would be if the pedestal value is correlated with the gain. There was concern about the resistor tracks crossing the diode metal line as this could cause feedback. (It was not known if this would be positive or negative feedback.) The track should go up to a metal layer for this crossing; the loss of resistance will be very small. Also, Jamie should explicitly crosscheck the capacitance between the resistor and the diode metal line. With this change, it was decided the extra area of resistor was worth keeping. The resistor strips are currently connected at the ends using metal. A small gain of ~5% might be possible by using polysilicon to make these connections also. This may also allow the resistor lines to be placed more evenly spaced, potentially even allowing another pair of lines to be added. Change request 2: The discussion (above) already listed several test structures which would be useful. This change request is to use an unpopulated area which can fit 15 I/O pads and include test structures between them. The pads do not currently exist so there is no connection for them on the PCB. The most obvious way to use them is then to probe them directly. The pads could probably only be probed if the sensor is not wire-bonded so this would not be done on sensors mounted to PCBs. Rebecca Coath will design this region and she (with Jamie) will come up with a proposal for test structures which will use the 15 pads. Problem report 5: The crosstalk is thought to be due to coupling through the power supplies and so separating the comparator and monostable power grids should help. However, this is not definitely the cause so there is some risk the crosstalk will not be cured by this change. However, there is no significant downside to this so it should be done. Problem report 3: This is also discussed on pages 6-15 of the support document. Mark pointed out that the standing current could have pulled up the the substrate and hence increased the crosstalk. If this effect was significant, then the new design should also help with crosstalk reduction. The pixel "twinning" effect, where masked pixels give hits when other particular are unmasked, is not fully understood. It could be due to this memory corruption but may not be entirely from this. It requires further dedicated tests with a single unmasked pixel to narrow down the causes. Test pixels: These are discussed on pages 16-17 of the support document. It was decided that the two "live" pixels should be separated and each should be surrounded by dummy pixels, so giving two 3x3 arrays rather than one 3x4 array. The two live pixels should have the design used in the bulk in one and the ASIC V1 design in the other. Higher levels: These are discussed on page 18 of the support document. The I/O pads have been increased from 60mu to 80mu in both directions. This is effectively the limit in either direction. The metal layers for the power mesh are already at the limit of their capacity and will not be adjusted any further. Hi-res changes: There are two changes needed for the hi-res epitaxial layer option; all n-wells need to be protected by deep p-well (or spaced further apart, which is not feasible) and a guard ring to protect the pixels from stray charge should be added. The deep p-well under the n-wells is essential to prevent latch-ups. Renato stated the depletion layer would extend ~20mu from the signal diodes and so would not extend fully under the memory areas. Hence, any charge deposited under most of the memory would see no electric field and hence diffuse or recombine. This would make it less of a problem and so it was thought reasonable to add deep p-well in this region. A guard ring will be added around the outside of the bulk region. The test pixels will have a separate guard ring. These will be electrically connected to the same bond pad (the one previously used for the sampler V_reset). It was thought unnecessary to have a guard ring outside the pads to collect charge from the edges (e.g. due to microcracks from wafer dicing), but Renato and Jamie should check this with the foundry. Completion of design: Jamie hopes to have completed most, if not all, of the remaining design by the time of the next MAPS meeting, which is on Wed 25 Jun. Hence, this should be a good time to do a final sign-off on the new design.