CALICE MAPS Final Design Review 3, RAL, 27/02/09 ================================================ Present: Jamie Crooks, Paul Dauncey, Mark Prydderch, Renato Turchetta, Mike Tyndel Minutes: Paul Jamie welcomed Mark as the external reviewer for the FDR for TPAC1.2. There are three problem reports which are not being acted on in the new design. These are o PR2: This is the "pickup" effect which causes extra pixels to fire when too many are enabled and fire at the same time. It is not clear if a fix for this would be possible and it would certainly require changes to a larger number of masks. o PR4: This is due to the routing of the test pixel lines which take signals from the internal nodes to the outside. Hence, it does not apply to the bulk pixels. o PR5: This can be reliably overcome using the external power modules. There are enough of these for all foreseen TPAC1.2 tests. PR1 is the row address problem which is definitely diagnosed and can be easily fixed. Both the schematic and layout were wrong previously so they were internally consistent. Both have now been modified. PR3 describes the feedback which causes the pixel to oscillate at low thresholds. The metal layer to shield the signal was added to the lower left area of the pixel following the FDR for TPAC1.1, but the upper left area was missed in the review. The shield added is connected to the analogue ground and hence is not connected to the digital power level close by. Jamie showed some slides to go through the known issues with the TPAC1.1 design; see FDR web page. Slide 10 gives gain values from the schematic of 136uV/e- for TPAC1.1 and 160uV/e- for TPAC1.2, although the schematic should not have changed. Jamie will check whether this is a real effect or an error. [Note added after the review: The discrepancy between the stated gains for the TPAC1.1 and TPAC1.2 schematic pixels have been checked, and should both read 136uV/e-. The larger stated figure (160uV/e-) can be reproduced in simulation if one omits the 14fF diode-node parasitic capacitance in the schematic. This is a simple simulation setup error; there is nothing of concern regarding the submission.] Slide 11 showed a new effect found the day previously. This coupling was removed in TPAC1.1 (and hence will also not be present on TPAC1.2) due to rerouting the signal line to the left, rather than the right, of the central pixel region. Jamie has not seen this effect on the test pixel but this may be due to the external signal traces coming out at a different point in the test pixel from the bulk (which is the one which is simulated and shows the capacitance). Jamie will run an RCX on the test pixel design to check for this. [Note added after the review: The review highlighted that a predicted injection effect in the TPAC1.1 test pixel (of V1.0 preShape) was not present, causing some concern whether RCX simulations could be believed. On further investigation Jamie saw that the signal causing the injection is broken and routed out to the test pad BEFORE it interacts with the analogue node. Therefore the test pixel is indeed not expected to show an injection, as previously stated. This no longer contradicts RCX simulations, and does not impact the TPAC1.2 submission.] On slide 15, the number of polygons observed to have changed on the CS layer is used to deduce a total of 408 bits having changed (i.e. 816 changes as each changed bit requires one connect and one disconnect to the power and the ground rails). It is not known if the value of 408 bits is correct for changing Gray codes 0-83 to 84-167 and this will be checked by Paul. [Note added after the review: 408 is indeed the correct number.] There were two yield issues with TPAC1.1. There was a very low bonding yield during a particular period, when TPAC1.0 sensors would work but not TPAC1.1 sensors. This has since gone away so was thought to be a problem with the bonder setup. The second yield problem was with shorts between power and ground, which affected 50% of sensors. This was common to all wafers and splits. It is thought it was a processing issue at the foundry although they have never supplied the data to check this. It might be due to violation of the design rules for the n-well minimum spacing; it is supposed to be at least 2.8mu, but some n-wells in TPAC are only 2.4mu apart. However, this rule is also violated by the pad library designs supplied by the foundry which have been used with no problems previously. Jamie will submit the design next week and it is expected to take eight weeks, meaning the sensors will be returned around the end of Apr or the beginning of May. He assumes the foundry will do a complete DRC check even though most of the masks have not changed. There is a minimum order of 12 wafers, of which we already had 9 on hold from the TPAC1.1 order. Each wafer will hold 20 sensors. The splits will be ============================================================== Qty Starting Material DPW Comment ============================================================== 3 Standard 12um EPI Yes Held from TPAC1.1 shuttle 3 Standard 12um EPI No 3 Hi-Res 12um EPI Yes Held from TPAC1.1 shuttle 3 Hi-Res 18um EPI Yes Held from TPAC1.1 shuttle ============================================================== Paul signed the Change Request form at the end of the review.