CALICE MAPS Interim Design Review 1, Part 1, RAL, 19/12/06 ========================================================== Present: Jamie Crooks, Paul Dauncey, Nicola Guerrini, Mark Prydderch, Renato Turchetta, Mike Tyndel Notes: Paul Each part of the design was discussed in turn. The following are notes on particular points raised. The page numbers correspond to the document versions available during the review. There were several places in the documents where older numbers or only qualitative results were given as the design had progressed since they were written. Jamie will update all the documents and release a consistent set. Shaper pixel: The monostable output pulse length can be adjusted externally. It is asynchronous to the sampling clock and so can give more than one hit if the pulse length is longer than the clock period. This is much preferable to missing a hit due to the pulse length being too short, so it is probably we will run with a average monostable length ~10-20% longer than the clock period. The nominal signal size assuming deep p-well is 800e-, which gives a 120mV output from the preamp. Pg 4, fig 2: There is a varying offset on the level before the signal. The sensor output is not affected but this could affect absolute values like the dynamic range, etc. Its source should be checked. Pg 5 onwards: The figures here show "numele" which is the number of e- injected per diode. The total signal is therefore four times this value. The injected current signal is modelled, from Giulio's simulation, as a fast-rising edge followed by a slower exponential-like falloff. Jamie could not remember the fall-off time constant but it was assumed to be related to the diffusion and hence would be of order 100ns; Jamie will check this with Giulio. The diode charge is then the integral of this current. There was a concern that the power supply might shut off for very large signals (>10k e-), when the shaper saturates. This should be checked. Pg 8: Signal will push up the operating point of the shaper and so could potentially saturate it during a bunch train, although this should be rare as the signal rate is low. The diode dark current will continuously do the same thing. Renato reported that a good diode should have a dark current of ~ 10k e-/sec. Hence, over a 2ms bunch train, this would give 20e- per diode, which is negligible. Pg 9: The section "Improving Overflow" was not implemented as it was found to introduce too much noise. Pg 10: The comparator power values are obsolete; the table should be updated (and similarly for the equivalent sampler table). Pg 13: The noise of 3.5mV ~ 23e- is for the 1.8x1.8mu2 diode layout. This includes 8fF addition parasitic capacitance. There may be an additional contribution due to the reset transistors; this was thought likely to be small but could add up to an additional 1fF. All noise values quoted for the shaper (and sampler, below) are without any contribution from the comparator; see below. Note, Eldo gives a different value for the noise, specifically 2.5mV. The preamp and shaper are single-ended and so will be sensitive to noise through the power lines. External noise could be filtered to some degree, although space for capacitors off-sensor will be limited. One source could be wavefield effects from the beam, which are very significant for the vertex detector although should be less so for the calorimeter. Konstantin has done some work on this for LCFI and he may be able to get some estimates of the size of the effect. There could also be internal effects like the digital logic and monostable switching, which could affect neighbouring pixels also. No simulation has been done on this although it will be needed, in order to specify the limits on external noise filtering. Applying a sine wave to the power supply rail with a frequency ~1MHz should give a reasonable estimate. The main way to design in better power supply rejection would be to go to a differential preamp and shaper, which would take twice the power and would have a higher intrinsic noise, due to having twice as many components. It was decided to stay with the current design and change this for the second design if necessary. This should be a relatively low risk change, even though it would be a non-trivial effort, of order 1SM. The substrate will not require a direct ground, although we should test the sensor both with and without this. There will be an effective ground to the substrate from the top. Pg 14/15: The working point for the bias current can be selected externally, allowing the optimisation for the power vs. noise to be done after fabrication. Pg 16: The tables here (and for the sampler, below) should be made quantitative, rather than specifying high/medium/low risk. The most sensitive component appears to be the preamplifier capacitor, Cpre. This has a 2.0x1.6mu2 area and, being close to minimum, is sensitive to the exact edge structure and metal size. A 20% variation would give a 10% variation in the pixel noise; it would also affect the gain but this can be compensated by the per-pixel trim on the comparator. The capacitor specification from Tower gives the six sigma variation as +/-17%. There are three contributions; stray capacitance, oxide thickness and edge/area gemetric variations. The oxide thickness would be mainly uniform on a given sensor, but vary between sensors. To reduce the area effects, two larger 8fF capacitors in series could be used, so each has a smaller boundary variation, although the other contributions might increase. The benefit of this should be checked but the decision was to move to using two in series. Similarly, the shaper resistor rin could be made from two 200kohm resistors in parallel. It would be difficult to have a precise calibration circuit per pixel at the shaper input; the accuracy would be limited by the capacitance variations. The laser system will be needed to give a pixel-by-pixel calibration. Sampler pixel: Some of the comments above equally apply to the sampler design and are not repeated below. Pg 4: The circuit will take ~1us to power up before the bunch train. This should be sufficient as the sensors could then be staggered in their power-up times so as to spread the jump in current. As long as the total time is short compared with the bunch train length of 2ms, then the extra power will be small. Pg 6: The reset "error" is at most ~6mV (which is ~5% of the assumed signal size of 240mV) even for the largest signals considered, of order 20k e-. The working point limit is around 64k e- per bunch train. Pg 11: The noise value quoted, 5.7mV needs to be multiplied by sqrt(2) due to the effective double sampling, giving a total of ~8mV, which is equivalent to ~30e-. This again assumes the 1.8x1.8mu2 diodes. Note, Eldo gives a different value for the noise. (The actual value was not known in the review.) Pg 12: The shaper noise is less than the sampler noise for all parasitic capacitor values for the 3.6x3.6mu2 diode sizes. This size has a higher S/N than 1.8x1.8mu2 according to Giulio's latest simulations. Pg 17: The Cin and Cfb labels in the table are incorrectly swapped here. Again, the risk should be quantified. Pg 20: An analysis of the phase margins should be added. Comparing the two, then the sampler gives a higher noise overall but it is better controlled with respect to the process parameters, particularly Cfb. The circuits may need to be reoptimised when the input capacitance is more accurately known. Comparator: Pg 7: The longest delays in the signal from the shaper are removed by the comparator response time, so the overall effect is to change the effective threshold rather than shift the time of the small signal hits. Pg 8: There is no such effect for the sampler so the spread in time of hits will be up to ~1us. Pg 10: The comparator noise of ~2.8mV adds in quadrature with the other circuit contributions, although the gain of 1.5 for the compatator means the 2.8mV should be considered as 1.9mV when comparing with the other noise values. Using Eldo, the shaper noise increases from 2.5mV before the comparator to 4.0mV with the comparator. (Note the previous noise value quoted above was 3.5mV). The sampler gives 6.2mV with the comparator using Eldo. (The previous value quoted above was 8mV before the comparator, not using Eldo.) A summary of all noise values with and without the comparator, using both estimates, should be added to the documentation. Also, the expected noise rate vs. threshold should be plotted. Pg 13: The mismatch estimates do not take into account any layout features such as inter-digitation which can reduce the effects. Pg 15: The trim circuit gives ~30mV of adjustment over 16 values (i.e. 4 bits). This corresponds to ~2mV steps, so each is ~half the noise. The comparator power is effectively independent of the trim setting as it diverts the existing current; the mirror transistors take little power. Logic and top level: This was only discussed briefly; a full review will be held in the New Year, see below. The sensor will have eight arrays of 84x42 pixels, with four logic columns, each serving the 42 pixels in each row. There will be four variants of the pixel design and hence two arrays of each, giving a total of 84x84=7056 pixels per type. The total sensor then contains 168*168=28224 pixels. The logic columns will be an addition four pixels = 200mu wide. The switches needed for power pulsing are the four ENABLEn inputs. The output data multiplexer nominally runs at 1MHz and multiplexes four columns, each of 31 bits, within each clock tick. Hence, it effectively handles 16MBytes/s. It might be possible to run it faster by up to another factor of two. The next version will have a high speed serial I/O path but this has not been implemented; it would have to be done off-sensor for this round if required. It will not be possible to load an external pattern into the sensor memory and read this out. However, by loading specific masks and then forcing hits, it should be possible to test most parts of the memory. The mask and trim settings (5 bits/pixel) are loaded into the sensor through a serial input. The first bit for each of the 84x2=168 columns is loaded into a serial-to-parallel register and then shifted into the columns on a command. The next 168 bits are then serially loaded and shifted in, etc. This load-shift process is repeated 168x5=840 times for the complete sensor, giving a total of ~17kBytes. Jamie will add an output parallel-to-serial register at the other end of the sensor. This will capture the data with a parallel shift as they come out of the pixels and then shift them out serially so the data can be read out and checked. This will allow the previous (but not current) settings to be verified. All I/O pads will be single-ended, nominal 3.3V logic levels and will have input protection. There is an OR of the overflow condition wired to an output pad, so it is possible to detect this externally. However, it is currently the OR of the readout column, whereas it would be more useful to be an OR of all the pixels of one type as they may have quite different noise (and hence overflow) rates. Part 2 of this IDR, to cover the logic and top level schematics, will be held at a future date, TBD. Matt Noy and Marcel Stanitzki were suggested as referees, although an external referee will be needed in addition.