CALICE MAPS Preliminary Design Review 2, RAL, 01/05/08
======================================================
Present: Jamie Crooks, Marcel Stanitzki, Renato Turchetta, Mike Tyndel
By phone: Paul Dauncey, Matt Noy

Notes: Paul


Discussion: Mike raised several points for clarification:
 o The "twinned pixels" observed by Owen are thought to be more than
   just corruption. As such, they will not necessarily be cured by the
   bug fixes proposed.
 o The gain of the samplers is thought to be low by around a factor
   of two. The same may be true of the shapers also. This is not
   understood and so unless the cause is found, this will not be fixed.
 o The trim DAC range can be adjusted externally. The trim settings
   cannot be made to be non-destructively readable without significant
   extra work. There is a program from Matt (SensorLoad) which can test
   the load and readback independently of the DAQ. Jamie has found this
   rarely reports errors.
 o The noise is not yet measured and there are no analogue measurements
   from the bulk.
 o There should be more test pixels in the new sensor so as to be able 
   to surround the ones read out with others, more like the bulk. The
   minimum is four test pixels, but preferably twelve, i.e. two pixels
   which can be measured and then one on every side of these two, to
   make a 3x4 array.
 o There is interest to try making the new sensor on hi-resisitivity
   epitaxial layer wafers. The design should need little modification
   for this.


Project specification: Sec 2.1; Birmingham will not be involved in the
 next round of PCB assembly and so should be removed (page 3).


Technical specification: Sec 3; the bug fixes are unambiguous and so
 there are no issues.

 To fix the gain would be a big study. The main issue is to first
 confirm the gain really is a factor of two low for the samplers (and
 possibly shapers). This requires an absolute calibration which needs
 the combination of the RAL Fe55 source (to give the peak 6MeV position
 on the test structure) and the laser (to give the equivalent laser
 settings on the test structure and hence the equivalent signal in the
 bulk) but this has not yet been done.

 Sec 4.1; We will retain the two capacitor variants of the shapers.

 The bias lines will now supply twice the number of pixels. They carry
 no current so there should be no issues of droop or gradient across the
 sensor. In principle, the mirror match might get a little worse but
 this effect could be offset by the fact that the capacitive impedence
 will increase also.

 Sec 4.2; The wire bond pad sizes should be increased if possible to
 minimise the problems seen with the bonder hitting the passivation
 layer. The pad width is already at the maximum but the depth is not.
 The pads will be elongated to their maximum in depth. 

 Sec 4.2; Unused circuitry should not be left in place, but should be
 removed. The sampler pads will now be unused and should not be bonded.

 For the splits, the minimum is three wafers with 20 sensors/wafer and
 the cost is likely to be roughly 3k/split. The prioritised list for
 splits was decided as
    2 splits of 12mu epitaxial layer, deep p-well
    1 split  of 12mu epitaxial layer, no deep p-well
    1 split  of 12mu epitaxial layer, deep p-well, hi-resistivity
    1 split  of  5mu epitaxial layer, deep p-well

 Sec 4.3; Extra trim bits are needed but there does not seem to be much
 to be gained from trying to have non-uniform trim units. The design for
 the two extra trim bits will be done by Rebecca Coath. This will not
 require any change to the deep p-well layout.

 Sec 4.4; The issue of having deep p-well under the memory areas was
 raised. The ideal would be to have the same absorption in this area as
 the rest of the sensor, so the pixels neighbouring the memory would
 work in the same way as the others. However, because of the different
 layout of the memory, the same deep p-well pattern would not give the
 same charge absorption. The conservative approach is to leave the
 memory with no deep p-well.

 Sec 4.5; As discussed above, we should aim for 12 test pixels.

 Sec 5; The diagram needs modification given the changes to the pixel
 types.


Testing specification: It would be useful to have a list of the basic
 sensor tests done for each sensor after it is bonding.

 The list of source tests should now include Fe55.

 Sec 8.2; The software and firmware changes for the extra trim bits
  should be listed.

 The document should be updated by the people doing the tests (RAL/PPD
 for Sec 9, Imperial for Sec 10 and Birmingham for Sec 11) with best
 estimates of the numbers, based on experience so far.


Other documents: No comments.


FDR: This will be on Fri 13 June, starting at 10am. The external
 reviewer is not yet confirmed.