CALICE MAPS Meeting, RAL, 01/09/05 ================================== Present: Jamie Crooks, Paul Dauncey, Renato Turchetta, Mike Tyndel, Giulio Villani, Nigel Watson, John Wilson Minutes: Paul The point of this first meeting after the CALICE proposal was approved was to outline the basics of the project and define the broad scope and schedule. Overview of award: Paul showed the details of the PPARC grant awarded for the MAPS work (see transparencies). Despite extending the project compared with the original proposal into FY08/09, the schedule still looks very tight, particularly for the beam test period. Hence, we should be aware that further delays may cause problems. Simulation work: Nigel showed some results from simulation work done at Birmingham. The studies were carried out using the SLIC detector simulation (based on Geant4) for the SiD detector. The analogue silicon was as in the SiD05 geometry (330mu silicon, 4x4 mm2 pads, projective geometry, i.e. the same number of theta/phi bins in each layer). The MAPS study had ~50mu pixel pitch and 5mu (not 15mu) epitaxial layer thickness. They will try different pixel sizes next week, look at non-projective geometry, and change the epitaxial layer to 15 microns. Status of conceptual design: Paul also showed some slides summarising the current knowlegde of the ILC requirements and conceptual design of the MAPS-based ECAL detector. This was mainly a summary of the conceptual design document which was written last year. Nigel pointed out that one outcome expected from the recent Snowmass meeting was a set of assumptions for the ILC (bunch timing, luminosity, etc). The ones used by Paul should therefore be updated to this set. Nigel will look into this and report back on what he finds. Mike commented that pushing for very high efficiency (in terms of both active area and channel yield) can be very expensive. A study to determine the requirement for inefficiency should be done. It is known from work done by Jean-Claude Brient that allowing a realistic diode pad yield does not impact the jet resolution much. MI3 work: Jamie showed some transparencies on the work he is doing for the MI3 project, which were from the RAL Microelectronics Open Day on 28/06/05. Several features of his design are very similar to what is needed for CALICE, although there are some significant changes also. One change needed is for the DRAM. This will only sustain the memory for around 1ms without a refresh cycle, which might be tricky to implement in Jamie's current design. 1ms would not be adequate for CALICE purposes as the data will need to be stored for a significant fraction of the ~200ms between trains. Static RAM would be possible, but would take more components and hence surface area. Jamie had to be careful in distributing the analogue counter (Greycode) in his design as it counts at ~50MHz. This may be much less of an issue for CALICE as the count speed would correspond to the collision frequency within the train, which will be an order of magnitude slower. The sensors have been returned from fabrication and are currently being mounted on PCBs to start testing. Jamie estimates testing will be complete by the end of the year, at which point he can concentrate fully on CALICE. Scope: There was a lengthy discussion on what we could hope to achieve within the CALICE project so as to define the scope. The main points which were decided were: o We will not attempt stitching and so will be constrained to at most 2x2 cm2 sensors. o We should stick to "standard" processes so as to have a choice of foundries, even if this means the parameters (mainly epitaxial layer thickness) is not ideal for our purpose. o The possibility of putting large contact pads on top of the wafer to allow solder paste bonding (as used for BGA components) should be considered. If an attempt is made to implement this, standard wire bond pads should also be included around the edge as a backup. o It is important to verify the sensor simulation so that realistic and dependable simulations can be done to find the optimal sensor parameters. This will prevent us having to map out the complete parameter space with physical designs. o The full logical functionality required for a real sensor should be implemented, even if this requires enlarging the pixel size beyond the assumed 50x50 mu2 to fit the gates. The simulation would then be used to interpolate the results to an optimised sensor. o We should try to sample every pixel at the full ~200ns period as a starting point. If this proves difficult, it will be better to integrate in time rather than gang pixels in space, as the physics rate at the ILC will be low. Hence, longer shaping times or slower comparators would be the best compromise if this is needed. o Alternative reset schemes to reduce noise should be considered; how many are implemented remains to be decided. In particular, a charge leakage scheme with no explicit reset should be seriously considered. o It is not known how uniform the pixels will be and hence how many pixels can share a single threshold level. For the first design, a single threshold for the whole sensor will be used; it would be most convenient if this was implemented as a DAC so it could be easily scanned by software. Schedule: A rough schedule was drawn up; this was added as an extra slide in Paul's talk and is outlined below: o Feasibility study - continuing until end Dec 05 o First design - Start Jan 06 to end Dec 06 o First fabrication - Start Jan 07 to end Apr 07 o First basic tests - Start May 07 to end Jun 07 o First detailed tests - Start Jun 07 to end Mar 08 o Second design - Start Jul 07 to end Dec 07 o Second fabrication - Start Jan 08 to end Apr 08 o Second basic tests - Start May 08 to end Jun 08 o Second detailed tests - Start Jun 08 to end Mar 09 o Beam test PCB design and fabrication - Start Oct 07 to end Sep 08 o Beam test period - Start Oct 08 to end Mar 09 CALICE-UK meetings at Cambridge: There is a UK Steering Board meeting (for the PIs) on the afternoon of 8/9/05 and a general meeting all day on the 9/9/05. Nigel, Mike and Renato will not be able to attend the former in person but a phone connection will be available. Actions: The following actions were agreed: o Paul - make a basic list of assumptions and requirements from the discussion in this meeting o Nigel - circulate the Snowmass ILC standard parameters o Renato and Jamie - consider the implications of the items discussed in the meeting for the sensor design o Nigel and John - continue the simulation work at Birmingham to cover the items listed in Paul's slides o Giulio, Nigel and John - work on combining the GEANT4 simulation with a parametrisation of Giulio's detailed sensor simulation so as to get a more realistic detector simulation Next meeting: 13:00 on Mon 10 Oct at RAL, although people could meet over lunch from around noon onwards.