CALICE MAPS Meeting, RAL, 10/11/05
==================================
Present: Jamie Crooks, Paul Dauncey, Anne-Marie Magnan,
 Renato Turchetta, Giulio Villani, Nigel Watson

Minutes: Paul

Minutes of previous meeting: No corrections.


Sensor simulation: Giulio had circulated a document since the last
 meeting with some preliminary findings and showed an update during the
 meeting; both are available from the usual web page.

 He is now working with pixels and diode spaces half those of
 previously, i.e. 25mu pixels and 12.5mu diode spacing, giving four
 diodes per pixel. A total charge of around 1100 e- is seen within the
 nine pixels around the position the charge is deposited; as the total
 (for a 20mu epitaxial layer) for a MIP is expected to be 1600 e-, this
 implies a significant fraction of the charge diffuses outside the
 simulated 3x3 pixel array. As the diffusion length for this epitaxial
 thickness is around 120mu, this seems reasonable, although it might
 indicate a thinner epitaxial layer would be better.

 Of the observed 100 e-, around 400 e- is seen on the central pixel
 when summing over the four diodes. With a rough estimate of the noise
 being 20-40 e-, then (for noise of 40 e-) a five sigma threshold would
 be around 200 e-, corresponding to ~50% of a MIP. Giulio finds a
 threshold between 40% and 60% would give reasonable efficiency and not
 too large a rate of double hits, so this looks feasible.

 A pixel-to-pixel variation of the threshold will clearly affect the
 noise and efficiency rates. However, the uniformity across pixels of
 the process is very hard to predict. The plan is for many pixels to be
 controlled by a single threshold DAC so choosing this region size will
 be important. Experimentally, measuring the noise rate as a function
 of DAC setting once real sensors are produced will be straightforward.

 Giulio's simulation currently has no n-wells from the circuit itself.
 Jamie recommended something of the order of 10mu^2 of n-wells should
 be added; he suggested something like a 3x3mu^2 square in the centre
 of the pixel for now as there is no more detailed design yet. For
 comparison, the diodes he simulates 1.5x1.5mu^2 = 2.25mu^2 so four
 diodes gives 9mu^2 total area. Hence, the circuit n-wells would be the
 same area as the diodes.

 The charge collection time is around 200ns, which is longer than the
 worst-case ILC bunch crossing (i.e. comparator sampling) time. This
 might either mean there would be charge from one MIP showing up in two
 consecutive samples or that the sample might have to occur before all
 the charge is collected. This depends on the reset scheme used to some
 extent as the charge has to be cleared somehow.

 The next steps are to repeat the simulation with circuit n-wells and
 then try a 10mu epitaxial layer with and without these n-wells.
 Following this, a simulation with one diode per pixel would be useful.
 Each simulation run takes around 10 days for the computations (mainly
 due to the huge volume being simulated).


Noise rates: Renato showed some slides of noise rate calculations which
 are available on the usual web page.

 He has assumed 600 e- signal in a pixel, which is somewhat more than
 Giulio's values (above) but close enough for this study. He sets a
 threshold at various factors (3-6) of the noise and sees the expected
 rate vary very strongly as a function of the cut, as expected.

 The calculation actually gives the number of times the comparator will
 give a rising edge per second. Our readout will effectively sample the
 comparator output per bunch crossing and so the number needed is the
 probability of the comparator being high at any time. This requires
 both the rate as calculated by Renato and the time for which the
 comparator then stays high. He assumed a bandwidth of 1-100MHz, so
 the "central" frequency of that range is 10MHz, which corresponds to a
 period of 100ns. Assuming this is the average time the comparator
 stays on, then Renato's numbers can be converted into probabilities by
 multiplying by 10^-7 sec. This gives noise rates of order 10^-15 for a
 six sigma threshold, 10^-10 for five sigma, 10^-6 for four sigma and
 10^-3 for three sigma. Some of these are substantially less than
 obtained by a naive Gaussian integration above the relevant threshold
 level, which would be 1.0x10^-9 for six sigma, 2.9x10^-7 for five sigma,
 3.2x10^-5 for four sigma and 1.4x10^-3 for three sigma and the
 difference should be understood.

 Assuming Renato's estimates of the bandwidth are correct, then the low
 end of 1MHz, i.e. 1us period, is longer than the sampling time of
 150ns. This means for noise of this frequency, the comparator is
 likely to stay high for O(10) samples, giving a correlated set of
 noise hits in a row. This could swamp the hit memory storage locations
 and so if this is a realistic likelihood, ways to limit the low end of
 the frequency range should be considered.


Other items; Jamie showed some slides of various issues and suggestions
 he had been considering; these are available from the usual web page.
 
 XFAB have a "standard" (now frozen) XC035 process which Jamie is set
 up to use. This will remain available for several years. However,
 there is a higher voltage version, XH035, which we might be interested
 in using. One application might be to bias the diodes to ~12V while
 keeping the circuit n-wells ~2V so as to improve the signal charge
 collection efficiency.

 The XH035 process is not (yet) certified for stitching. We had
 previously decided that we would not investigate or use stitching for
 this project. However, Jamie pointed out that the cost for using it is
 minimal and that it could be very useful for testing the use of long
 control lines. The obvious size to aim for would be something close to
 the 6x6cm^2 diode pad wafers in use in the current CALICE ECAL
 prototype.

 Flip-chip bump bonding looks feasible (and not too expensive) with
 only widely spaced edge pads. The minimum pitch size is 250mu, which
 sounds feasible, although there is no estimate of the numbers of
 connections needed yet.

 The expected data rate has an obvious influence on the time to read
 all data after a bunch train. Jamie estimates flushing the data from
 the pixels to a buffer on the edge of the sensor could be done in less
 than 1ms, which would imply he could continue to use DRAM rather than
 changing to SRAM. The latter will use more n-wells (and hence absorb
 more signal charge) and would take more pixel area.

 Jamie also pointed out that the power required just to drive each
 clock or data line across the sensor would exceed the power
 requirement needed to be competitive with the diode pad ASIC.


Items from the DESY meeting: Paul reported on various items, see the
 web page for the slides.

 The power value quoted in the requirements in (unfortunately) not
 wrong. To keep the comparators within the requirement (not allowing
 for any other power sources) then they would need to be turned on for
 only 10ns in each beam crossing.

 The suggestion made by Jamie to subdivide trains into several
 subtrains and allow only one hit in each seems to give much higher
 overflow rates than the original scheme. However, it looks like only
 6 or 8 timestamp memory locations may be needed, rather than the 16
 previously assumed.

 The French groups are pushing for a high-tech 1.5m PCB design with
 stitching and embedded components. We should probably meet with them
 in Paris to discuss the power issues and how many of these PCB
 concepts are realistic.


Next meeting: Fri 9 Dec in the R76 microelectronics meeting room,
 starting at 13.00. People arriving early can meet for lunch
 beforehand.