CALICE MAPS Meeting, RAL, 09/12/05
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Present: Jamie Crooks, Paul Dauncey, Renato Turchetta, Nigel Watson

Minutes: Paul


Minutes of previous meeting: No changes. Paul noted the differences
 between Renato's noise calculation and the naive Gaussian integral
 estimates. For a six sigma threshold they differ by six orders of
 magnitude although the difference disappears when reduced to three
 sigma. We are aiming for a noise rate in the range 10^-6 to 10^-5;
 Renato's calculation gives 10^-6 at four sigma while the naive estimate
 is within this range between four and five sigma. Hence, a four-to-five
 sigma threshold does seem a reasonable estimate to aim for, despite the
 differences in the exact rates expected.

 Paul raised an issue discussed at the previous meeting concerning the
 power required to drive a single clock line which Jamie estimated at
 6.4uW/mm^2, which is above the whole pixel power budget. This arises
 from the need to charge the clock lines and hence is due to their
 capacitance. In principle, pure capacitance does not consume power so
 would it be possible to drive the lines to take advantage of this?
 Jamie thought this would be hard; it would need current-driven lines 
 and hence a substantial redesign. Setting up an LC circuit with a
 frequency equal to that needed for the clock would be even harder; this
 inductance would not be possible to build into the MAPS. The power
 budget is not yet well defined, as it is a target (not achieved) for
 the analogue ASIC so we should not feel too constrained by this for the
 first sensor round.


Design ideas: The rest of the meeting was taken up with a detailed
 discussion of a lot of issues which have arisen as Jamie has been
 thinking through the design (see transparencies on the usual web page).

 A couple of the issues discussed beyond the transparencies were:
 o Jamie put together a spreadsheet giving an estimate of the data
   volume for various assumptions on noise and event rates. This shows
   the data could be transfered out in around 5ms, which is comparable
   with the best DRAM lifetimes. Hence, the DRAM timing is somewhat
   marginal. With DRAM, then a 50x50mu^2 pixel could fit a memory of
   16 bits x 4 locations. However, SRAM is significantly bigger and
   requires n-wells also, which will reduce the charge collection
   efficiency. In future, with smaller feature sizes (i.e. 0.18mu in a
   couple of years), it is not obvious if the capacitance per unit area
   drops as both the plate area and separation change. This means the
   DRAM lifetime will not necessarily degrade as the size goes down, at
   least at the rate naively expected.
 o A reset scheme was discussed with a hard reset just before the bunch
   train and then no reset throughout the train. This depends on how
   fast the charge would leak off during the time of the bunch train,
   which may be up to ~2ms. This was thought feasible; the simulation is
   unlikely to get this level of detail correct but it could be as low
   as ~1000e- per sec. This then gives two interesting options; to do
   this hard reset only and use a tracking comparator or to do a wired
   (continuous) reset throughout the train, again with a tracking
   comparator. 


Next meeting: Given the various people who could not attend this
 meeting, a date was not fixed. The people present could make any of
 Jan 19, 20, 25, 27. Paul will contact the others and fix a date.

 [Note added after the meeting: the date was fixed for Fri 20 Jan, 1pm.]